DS99R103TSQX/NOPB ,3-40MHz DC- Balanced 24-Bit LVDS Serializer 48-WQFN -40 to 85Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS99R106VS , 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
DS99R124QSQ , 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
DS99R124QSQX/NOPB ,5 SNLS318D –JANUARY 2010–REVISED APRIL 2013PIN DESCRIPTIONSPin Name Pin # I/O, Type DescriptionFPD-L ..
DS99R421 ,5-43 MHz FPD-Link LVDS (3 Data + 1 Clk) to FPD-Link II LVDS (Embedded Clk DC-Balanced) Conv 36-WQFN FEATURES DESCRIPTIONThe DS99R421 converts a FPD-Link input with 42• 5 MHz–43 MHz Embedded Clock & D ..
DS99R421QSQX/NOPB ,5-43 MHz FPD-Link LVDS (3 Data + 1 Clk) to FPD-Link II LVDS (Embedded Clk DC-Balanced) Conv 36-WQFN -40 to 105FEATURES DESCRIPTIONThe DS99R421 converts a FPD-Link input with 42• 5 MHz–43 MHz Embedded Clock & D ..
ED1402 ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402B ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402C ,NPN general purpose transistor
ED1402E ,NPN general purpose transistor
DS99R103TSQX/NOPB
3-40MHz DC- Balanced 24-Bit LVDS Serializer
DS99R103, DS99R104
www.ti.com SNLS241D –MARCH 2007–REVISED APRIL 2013
DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Checkfor Samples: DS99R103, DS99R104
1FEATURES DESCRIPTIONThe DS99R103/DS99R104 Chipset translatesa 24-
3 MHz–40 MHz Clock Embedded and DC- bit parallel bus intoa fully transparent data/control
Balancing 24:1 and 1:24 Data Transmissions LVDS serial stream with embedded clock information.
• Capableto Drive Shielded Twisted-Pair Cable This single serial stream simplifies transferringa 24-
User Selectable Clock Edge for Parallel Data bit bus over PCB traces and cableby eliminating the
skew problems between parallel data and clock
on both Transmitter and Receiverpaths.It saves system cost by narrowing data paths
• Internal DC Balancing Encode/Decode– thatin turn reduce PCB layers, cable width, and
Supports AC-Coupling Interface with no connector size and pins.
External Coding RequiredThe DS99R103/DS99R104 incorporates LVDS
• Individual Power-Down Controls for both signalingon the high-speed I/O. LVDS providesa low
Transmitter and Receiver power and low noise environment for reliably
• Embedded Clock CDR (Clock and Data transferring data overa serial transmission path. By
Recovery) on Receiver and no External Source optimizing the serializer output edge rate for the
Reference Clock Needed operating frequency range EMIis further reduced.
All Codes RDL (Random Data Lock)to Support In addition the device features pre-emphasisto boost
Live-Pluggable Applications signals over longer distances using lossy cables.
Internal DC balanced encoding/decodingis usedto
• LOCK Output Flagto Ensure Data Integrityatsupport AC-Coupled interconnects.
Receiver Side Balanced TSETUP/THOLD Between RCLK and
RDATA on Receiver Side PTO (Progressive Turn-On) LVCMOS Outputs Reduce EMI and Minimize SSO Effects All LVCMOS inputs and control pins have
internal pulldown On-Chip Filters for PLLs on Transmitter and
Receiver Integrated 100Ω Input Termination on Receiver Drive Packages Process 3.3V± 10%to
