DS92LV1212TMSA ,16 MHzFunctional Descriptionclock, the LOCK output will go low. When LOCK is low theThe DS92LV1212 is a 1 ..
DS92LV1224TMSA ,40 MHz-66MHz 10-Bit DeserializerDS92LV1023 and DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer and DeserializerJune 2002DS92LV1023 ..
DS92LV1224TMSA/NOPB ,30-66 MHz 10-Bit Deserializer 28-SSOP -40 to 85Functional DescriptionThe DS92LV1224 is a 10-bit Deserializer device which together with a compatib ..
DS92LV1224TMSA/NOPB ,30-66 MHz 10-Bit Deserializer 28-SSOP -40 to 85 SNLS189A –APRIL 2005–REVISED APRIL 2013After determining which clock edge to use, a start and stop ..
DS92LV1224TMSAX ,40 MHz-66MHz 10-Bit DeserializerGeneral Description®put pins into TRI-STATE to achieve a high impedanceThe DS92LV1023 transforms a ..
DS92LV1260TUJB ,six 1 to 10 deserializersElectrical Characteristics (Continued)Basic functionality and specifications per deserializer chann ..
DS92LV1212TMSA
16 MHz
DS92LV1212
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
with Embedded Clock Recovery
General DescriptionThe DS92LV1212isan upgradeofthe DS92LV1210.It
maintainsallofthe featuresofthe DS92LV1210withthead-
ditional capabilityof lockingtothe incoming data stream
without the needof SYNC patterns. This makes the
DS92LV1212 usefulin applications wherethe Deserializer
mustbe operated “open-loop”—withouta feedback path
fromthe Deserializertothe Serializer. The DS92LV1212is
designedtobe usedwiththe DS92LV1021 BusLVDS Serial-
izer. The DS92LV1212 receivesa Bus LVDS serial data
streamand transformsitintoa 10-bit wide parallel databus
and separate clock. The reduced cable, PCB trace count
and connector size saves cost and makes PCB layout
easier. Clock-to-dataand data-to-data skewsare eliminated
sinceone input receives both clock and databits serially.
The powerdownpinis usedto save powerby reducingthe
supply current whenthe deviceisnotin use. The Deserial-
izerwill establish locktoa synchronization pattern within
specifiedlock times butit canalsolocktoa datastreamwith-
out SYNC patterns.
Features Clock recovery without SYNC patterns-random lock Guaranteed transition every data transfer cycle Chipset(Tx+Rx) power consumption< 300mW (typ)@
40MHz Single differentialpair eliminates multi-channel skew 400 Mbps serialBus LVDS bandwidth(at40 MHz clock) 10-bit parallel interfacefor1 byte data plus2 controlbits UTOPIAI Interface Synchronization modeand LOCK indicator Flow-through pinoutfor easy PCB layout High impedanceon receiver inputs when powerisoff Programmable edge triggeron clock Footprint compatible with DS92LV1210 Small 28-lead SSOP package-MSA
Block DiagramTRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
DS100982-1
April 1999
DS92L
V1212
MHz
10-Bit
Bus
VDS
Random
Lock
Deserializer
with
Embedded
Clock
Recovery 1999 National Semiconductor Corporation DS100982
