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DS92LV010ATMX/NOPB-DS92LV010ATMXNOPB
Bus LVDS 3.3/5.0V Single Transceiver 8-SOIC -40 to 85
DS92LV010A
www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
Checkfor Samples: DS92LV010A
1FEATURES DESCRIPTIONThe DS92LV010Ais oneina seriesof transceivers
Bus LVDS Signaling (BLVDS) designed specifically for the high speed, low power
• Designed for Double Termination Applications proprietary bus backplane interfaces. The device
Balanced Output Impedance operates froma single 3.3V or 5.0V power supply
and includes one differential line driver and one
• Lite Bus Loading 5pF Typical receiver. To minimize bus loading the driver outputs
• Glitch Free Power Up/Down (Driver Disabled) and receiver inputs are internally connected. The
• 3.3Vor 5.0V Operation logic interface provides maximum flexibility as4
separate lines are provided (DIN, DE, RE, and
• ±1V Common Mode Range ROUT). The device also features flow through which
• ±100mV Receiver Sensitivity allows easy PCB routing for short stubs between the
• High Signaling Rate Capability (Above 100 bus pins and the connector. The driver has 10 mA
Mbps) drive capability, allowingit to drive heavily loaded
backplanes, with impedanceas lowas27 Ohms.
• Low Power CMOS Design Product Offeredin8 Lead SOIC Package The driver translates between TTL levels (single-
ended)to Low Voltage Differential Signaling levels.
• Industrial Temperature Range Operation This allows for high speed operation, while
consuming minimal power with reduced EMI. In
addition the differential signaling provides common
mode noise rejectionof ±1V.
The receiver threshold is ±100mV overa ±1V
common mode range and translates the low voltage
differential levelsto standard (CMOS/TTL) levels.
CONNECTION DIAGRAM
Figure1. SOIC Package
See Package Number D0008A
