DS90LV032ATMTCX ,3V LVDS Quad CMOS Differential Line Receiverapplications.Connection Diagram Functional DiagramDual-in-LineDS100067-1Order Number DS90LV032ATMor ..
DS90LV032ATMX ,3V LVDS Quad CMOS Differential Line ReceiverFeatures- High impedance LVDS inputs with power-off - Accepts small swing (330 mV) differential sig ..
DS90LV032ATMX NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Features 3 DescriptionThe DS90LV032A is a quad CMOS differential line1• >400 Mbps (200 MHz) Switchi ..
DS90LV032ATMX/NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Block Diagram... 104 Revision HistoryNOTE: Page numbers for previous revisions may differ from page ..
DS90LV032ATMX/NOPB ,3V LVDS Quad CMOS Differential Line Receiver 16-SOIC -40 to 85Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do no ..
DS90LV047A ,3V LVDS Quad CMOS Differential Line Driverapplications requiring ultra low power n Flow-through pinout simplifies PCB layoutdissipation and h ..
DS90LV032ATMTCX
3V LVDS Quad CMOS Differential Line Receiver
DS90LV032A LVDS Quad CMOS Differential Line Receiver
General DescriptionThe DS90LV032Aisa quad CMOS differentialline receiver
designedfor applications requiring ultralow power dissipa-
tionand high data rates.The deviceis designedto support
data ratesin excessof400 Mbps (200 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90LV032A acceptslow voltage (350mV typical)dif-
ferential input signalsand translates themto3V CMOSout-
put levels.The receiver supportsa TRI-STATE® functionthat
maybe usedto multiplexoutputs. Thereceiver alsosupports
open, shortedand terminated (100Ω)inputFail-safe.There-
ceiver outputwillbe HIGHforall fail-safe conditions.
The DS90LV032A and companion LVDSline driver (eg.
DS90LV031A) providea new alternativeto high power
PECL/ECL devicesfor high speed point-to-point interface
applications.
Features >400 Mbps (200 MHz) switching rates0.1ns channel-to-channel skew (typical)0.1ns differential skew (typical)3.3ns maximum propagation delay 3.3V power supply design Power down high impedanceon LVDS inputs Low Power design (40mW 3.3V static) Interoperable with existing5V LVDS networks Accepts small swing (350mV typical)VID Supports open, shortand terminated input fail-safe Compatible with ANSI/TIA/EIA-644 Industrial temp. operating range (-40˚Cto +85˚C) Availablein SOICand TSSOP Packaging
Connection Diagram Functional Diagram
ENABLES INPUTS OUTPUT EN* RIN+ −RIN− ROUT X Z
All other combinations VID≥ 0.1V H ENABLE inputs VID≤ −0.1V L
Full Fail-safe
OPEN/SHORT H Terminated
Dual-in-LineDS100067-1
Order Number DS90LV032ATM DS90LV032ATMTC
SeeNS Package Number M16Aor MTC16DS100067-2
July 1999
DS90L
V032A
VDS
Quad
CMOS
Differential
Line
Receiver©1999 National Semiconductor Corporation DS100067
