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DS90LV001TLD-DS90LV001TM-DS90LV001TMX Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
DS90LV001TLDNSN/a857avai3.3V LVDS-LVDS Buffer
DS90LV001TMNS ?N/a40avai3.3V LVDS-LVDS Buffer
DS90LV001TMXNSN/a5000avai3.3V LVDS-LVDS Buffer


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DS90LV001TLD-DS90LV001TM-DS90LV001TMX
3.3V LVDS-LVDS Buffer
DS90LV001
3.3V LVDS-LVDS Buffer
General Description

The DS90LV001 LVDS-LVDS Buffer takesan LVDS input
signal and providesan LVDS output signal.In many large
systems, signals are distributed across backplanes, and onethe limiting factorsfor system speedisthe ’stub length’or
the distance between the transmission line andthe untermi-
nated receiverson individual cards. Althoughitis generally
recognized that this distance shouldbeas shortas possible maximize system performance, real-world packaging con-
cerns often makeit difficultto makethe stubsas shortasthe
designer would like.
The DS90LV001, availableinthe LLP (Leadless Leadframe
Package) package,will allowthe receivertobe placed very
closetothe main transmission line, thus improving system
performance. wide input dynamic range will allow the DS90LV001to
receive differential signals from LVPECLas wellas LVDS
sources. This will allow the deviceto alsofillthe roleofan
LVPECL-LVDS translator. output enable pinis provided, which allows the userto
placethe LVDS outputin TRI-STATE.
The DS90LV001is offeredin two package options,an8pin
LLP and SOIC.
Features
Single +3.3V Supply LVDS receiver inputs accept LVPECL signals TRI-STATE outputs Receiver input threshold< ±100 mV Fast propagation delayof 1.4ns (typ) Low jitter 800 Mbps fully differential data path 100ps (typ)of pk-pk jitter with PRBS=223−1 data
patternat 800 Mbps Compatible with ANSI/TIA/EIA-644-A LVDS standard8pin SOIC and space saving (70%) LLP package Industrial Temperature Range
Connection Diagram
Block Diagram
Top View

DS101338-5
Order Number DS90LV001TM, DS90LV001TLD
See NS Package Number M08A, LDA08A

DS101338-2
April 2001
DS90L
V001
3.3V
VDS-L
VDS
Buffer
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