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DS90CR288MTD
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver
DS90CR288
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link Receiver- 75 MHz
General DescriptionThe DS90CR287 (see DS90CR287/288A datasheet) trans-
mitter converts28 bitsof CMOS/TTL data into four LVDS
(Low Voltage Differential Signaling) data streams.A phase-
locked transmit clockis transmittedin parallel with the data
streams overa fifth LVDS link. Every cycleof the transmit
clock28 bitsof input dataare sampled and transmitted. The
DS90CR288 receiver converts the four LVDS data streams
back into28 bitsof CMOS/TTL data.Ata transmit clock
frequencyof75 MHz,28 bitsof TTL data are transmittedat rateof 525 Mbpsper LVDS data channel. Usinga75 MHz
clock,the data throughputis 2.10 Gbit/s (262.5 Mbytes/sec).
Complete specificationsfor the DS90CR287 are locatedin
the DS90CR287/DS90CR288A datasheet. The DS90CR287
supports clock rates from20to85 MHz.
This chipsetisan ideal meansto solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features20to75 MHz shift clock support 50% duty cycleon receiver output clock Best-in-Class Set& Hold Timeson TxINPUTs and
RxOUTPUTs Low power consumptionTx+Rx Powerdown mode <400μW (max) ±1V common-mode range (around +1.2V) Narrow bus reduces cable size and cost Upto 2.10 Gbps throughput Upto 262.5 Mbytes/sec bandwidth 345 mV (typ) swing LVDS devicesfor low EMI PLL requiresno external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package
Block Diagrams
DS90CR287DS100872-1
Order Number DS90CR287MTD
SeeNS Package Number MTD56
(See DS90CR287/DS90CR288A datasheet)
DS90CR288DS100872-27
Order Number DS90CR288MTD
SeeNS Package Number MTD56May 2002
DS90CR288
+3.3V
Rising
Edge
Data
Strobe
VDS
28-Bit
Channel
Link
Receiver
MHz
