DS90CF384AMTDX/NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkElectrical Characteristics (continued)Over recommended operating supply and temperature ranges unle ..
DS90CF384MTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL ..
DS90CF384MTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramsTypical ApplicationDS012887-2®TRI-STATE is a registered trademark of National Semicon ..
DS90CF386MTD ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzFeaturessec bandwidth) back into parallel 28 bits of CMOS/TTLdatan 20 to 85 MHz shift clock support ..
DS90CF386MTDX ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85 MHzElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF386MTDX NOPB ,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) LinkBlock Diagrams. 174 Revision HistoryNOTE: Page numbers for previous revisions may differ from page ..
DS90CF384AMTD/NOPB-DS90CF384AMTDX/NOPB
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link
DS90CF364A, DS90CF384A
www.ti.com SNLS040I–JUNE 2000–REVISED APRIL 2013
DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link- 65
MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link- 65 MHz
Checkfor Samples: DS90CF364A, DS90CF384A
1FEATURES DESCRIPTIONThe DS90CF384A receiver converts the four LVDS
20to65 MHz Shift Clock Support data streams (Upto 1.8 Gbps throughput or 227
• 50% Duty Cycle on Receiver Output Clock Megabytes/sec bandwidth) back into parallel 28 bits
Best-in-Class Set& Hold Times on of CMOS/TTL data (24 bitsof RGB and4 bitsof
RxOUTPUTs Hsync, Vsync, DE and CNTL). Also availableis the
DS90CF364A that converts the three LVDS data
• Rx Power Consumption <142 mW (typ) streams (Up to 1.3 Gbps throughput or 170
@65MHz Grayscale Megabytes/sec bandwidth) back into parallel 21 bits
• Rx Power-down Mode <200μW (max) of CMOS/TTL data (18 bitsof RGB and3 bitsof
ESD Rating >7 kV (HBM), >700V (EIAJ) Hsync, Vsync and DE). Both Receivers' outputs are
Falling edge strobe.A Rising edgeor Falling edge
• Supports VGA, SVGA, XGA and Dual Pixel strobe transmitter (DS90C383A/DS90C363A) will
SXGA. interoperate witha Falling edge strobe Receiver
• PLL Requires no External Components without any translation logic.
Compatible with TIA/EIA-644 LVDS Standard The DS90CF384A/ DS90CF364A devices are
• Low Profile 56-leador 48-lead Packages enhanced over prior generation receivers and
provideda wider data valid time on the receiver
output.
This chipsetis an ideal meansto solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
BLOCK DIAGRAMS Figure2. DS90CF364A DGG-48
