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DS80C410-FNY |DS80C410FNYMAXIMN/a1500avai3.3 V, network microcontroller with ethernet and CAN
DS80C410-FNY |DS80C410FNYDALLASN/a2avai3.3 V, network microcontroller with ethernet and CAN


DS80C410-FNY ,3.3 V, network microcontroller with ethernet and CANELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) (Note 1) CC3 CC1 ..
DS80C410-FNY ,3.3 V, network microcontroller with ethernet and CANFEATURES  High-Performance Architecture The DS80C410/DS80C411 network microcontrollers offer Sing ..
DS80C410-FNY+ ,Network Microcontrollers with Ethernet and CANELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) (Note 1) CC3 CC1 ..
DS80C410-FNY+ ,Network Microcontrollers with Ethernet and CANFEATURES The DS80C410/DS80C411 network microcontrollers offer  High-Performance Architecture the h ..
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DS80C410-FNY
3.3 V, network microcontroller with ethernet and CAN
GENERAL DESCRIPTION The DS80C410/DS80C411 network microcontrollers offer
the highest integration available in an 8051 device. Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire® Master,
and 64 I/O pins. The DS80C410 and DS80C411 also include 64kBytes internal SRAM for user application
storage and network stack.
To enable access to the network, a full application-accessible TCP IPv4/6 network stack and OS are provided
in the ROM. The network stack supports up to 32 simultaneous TCP connections and can transfer up to 5Mbps through the Ethernet MAC. Its maximum system-
clock frequency of 75MHz results in a minimum instruction cycle time of 54ns. Access to large program or data memory areas is simplified with a 24-bit addressing
scheme that supports up to 16MB of contiguous memory.
To accelerate data transfers between the microcontroller and memory, the DS80C410 and DS80C411 provide four
data pointers, each of which can be configured to automatically increment or decrement upon execution of certain data pointer-related instructions. High-speed shift,
normalization, accumulate functions and 32-bit/16-bit multiply and divide operations are optimized by the DS80C410/DS80C411 hardware math accelerator.
The High-Speed Microcontroller User’s Guide and the High-Speed
Microcontroller User’s Guide: Network Microcontroller Supplement
should be used in conjunction with this data sheet. Download
both at: /user_guides.

APPLICATIONS

Industrial Control/Automation
Environmental Monitoring
Network Sensors
Data Converters (Serial-to-Ethernet, CAN-to-
Ethernet)
Vending
Home/Office Automation
Transaction/Payment Terminals
Remote Data-Collection
Equipment ORDERING INFORMATION
* Future product—contact factory for availability.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Magic Packet is a registered trademark of Advanced Micro
Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
FEATURES
High-Performance Architecture Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate Flat 16MB Address Space Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement 16/32-Bit Math Accelerator Multitiered Networking and I/O 10/100 Ethernet Media Access Controller (MAC)
Optional CAN 2.0B Controller 1-Wire Net Controller Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O Pins) Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP and TFTP
Full, Application-Accessible TCP/IP Network Stack Supports IPv4 and IPv6 Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler MAC Address can Optionally be Acquired from IEEE-Registered DS2502-E48 10/100 Ethernet Mac
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC (10Mbps) Interfaces Allow Selection of PHY Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet® and Wake-Up Frame Detection 8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU Half- or Full-Duplex Operation with Flow Control Multicast/Broadcast Address Filtering with VLAN
Support Full-Function CAN 2.0B Controller
15 Message Centers Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks Media Byte Filtering to Support DeviceNet™, SDS, and Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode Integrated Primary System Logic
16 Total Interrupt Sources with Six External Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic Interference (EMI) Programmable Watchdog Timer
Oscillator-Fail Detection Programmable IrDA Clock Features continued on page 35. Pin Configuration appears at end of data sheet.
Selector Guide appears at end of data sheet.
DS80C410/DS80C411
Network Microcontrollers with
Ethernet and CAN
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Input Pin Relative to Ground………………………………………………………..-0.5V to +5.5V
Voltage Range on Any Output Pin Relative to Ground……………………………………………..-0.5V to (VCC3 + 0.5)V Voltage Range on VCC3 Relative to Ground…………………………………………………………………..-0.5V to +3.6V
Voltage Range on VCC1 Relative to Ground…………………………………………………………………..-0.3V to +2.0V Operating Temperature Range………………………………………………………………………………..-40°C to +85°C
Junction Temperature……………………………………………………………………………………………..+150°C max Storage Temperature Range………………………………………………………………………………...-55°C to +160°C
Soldering Temperature………………………………………………………………See IPC/JEDEC J-STD-020 Standard
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
DC ELECTRICAL CHARACTERISTICS

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Note 1:
Specifications to -40°C are guaranteed by design and not production tested.
Note 2:
The user should note that this part is tested and guaranteed to operate down to VCC3 = 3.0V and VCC1 = 1.62V, while the reset
thresholds for those supplies, VRST3 and VRST1 respectively, may be above or below those points. When the reset threshold for a
given supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum
operating point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower
than the guaranteed minimum operating voltage, there exists a range of voltages for either supply, (VRST3 < VCC3 < 1.62V) or (VRST1
< VCC1 < 3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not
be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these
applications, it may be desirable to use a more accurate external reset.
Note 3:
While the specifications for VPFW3 and VRST3 overlap, the design of the hardware makes it such that this is not possible. Within the
ranges given, there is a guaranteed separation between these two voltages.
Note 4:
Current measured with 75MHz clock source on XTAL1, VCC3 = 3.6V, VCC1 = 2.0V, EA and RST = 0V, Port0 = VCC3, all other pins
disconnected.
Note 5:
While the specifications for VPFW1 and VRST1 overlap, the design of the hardware makes it such that this is not possible. Within the
ranges given, there will be a guaranteed separation between these two voltages.
Note 6:
Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-
6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
Note 7:
This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (VOH2). This
I/O pin state can be achieved by applying RST = VCC3.
Note 8:
The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (VOH1) remains in effect following the strong two-clock cycle
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Note 9:
Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition
of either WR or RD from a 0 to a 1.
Note 10:
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set
to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Note 11:
Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
Note 12:
During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the
Port 0 pin is driven by an external memory source.
Note 13:
The OW pin (when configured to output a 1) at VIN = 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
CRS, COL, MDIO) at VIN = 3.6V.
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)
Note 1:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
Note 2:
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3:
tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in
the External Clock Oscillator (XTAL1) Characteristics table.
Note 4:
The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5:
All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6:
For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid
bus contention.
Note 7:
References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not
for determing absolute signal timing with respect to the external clock.
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS

EXTERNAL CLOCK DRIVE
SYSTEM CLOCK TIME PERIODS (tCLCL, tCHCL, tCLCH) Note 1: Figure 21 shows a detailed description and illustration of the system clock selection.
Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the

minimum/maximum system clock high (tCHCL) and system clock low (tCLCH) periods are directly related to clock oscillator duty cycle.
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 1)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40 �C to +85°C.)
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