DS4404N+ ,Two/Four-Channel, I²C Adjustable Current DACELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, T = -40°C to +85°C.)CC APARAMETER SYMBOL CONDITIONS ..
DS4404N+TR , Two/Four-Channel, I2C Adjustable Current DAC
DS4412U+T , Dual-Channel, I2C Adjustable Sink/Source Current DAC
DS4420N+ ,I²C Programmable Gain Amplifier for Audio ApplicationsApplicationsABSOLUTE MAXIMUM RATINGSVoltage on V , SDA, and SCL Voltage on AV Relative to V ....... ..
DS4424N+ ,Two-/Four-Channel, I²C, 7-Bit Sink/Source Current DACApplications ♦ I C-Compatible Serial Interface♦ Two Address Pins Allow Four Devices on SamePower-Su ..
DS4432U+ ,Dual-Channel, I²C Adjustable Sink/Source Current DACApplications ♦ I C-Compatible Serial Interface♦ Low CostPower-Supply AdjustmentPower-Supply Margini ..
EC2-12NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-24 ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-24NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NJ ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5TNU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
DS4402N+T&R-DS4404N+
Two/Four-Channel, I²C Adjustable Current DAC
General DescriptionThe DS4402 and DS4404 contain two and four I2C
adjustable current DACs, respectively, that are each
capable of sinking or sourcing current. Each output has
31 sink and 31 source settings that are programmed by
the I2C interface. External resistors set the full-scale
range and step size of each output.
ApplicationsPower-Supply Adjustment
Power-Supply Margining
Adjustable Current Sink or Source
FeaturesTwo (DS4402) or Four (DS4404) Current DACsFull-Scale Range for Each DAC Determined by
External Resistors31 Settings Each for Sink and Source ModesI2C-Compatible Serial InterfaceTwo Three-Level Address Pins Allow Nine
Devices on Same I2C BusSmall Package (14-Pin TDFN)-40°C to +85°C Temperature Range2.7V to 5.5V Operation
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DACDC/DC
CONVERTER
OUT
SDA
SCLOUT0
OUT1
GND
RFS0RFS1
4.7kΩ4.7kΩVCC
VCCVOUT0
FS0FS1
R0B
R0A
DS4402
DC/DC
CONVERTER
OUT
VOUT1
R1B
R1A
Typical Operating Circuit
Ordering Information19-4641; Rev 3; 5/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
DS4402N+ -40°C to +85°C 14 TDFN-EP*
DS4402N+T&R -40°C to +85°C 14 TDFN-EP*
DS4404N+ -40°C to +85°C 14 TDFN-EP*
DS4404N+T&R -40°C to +85°C 14 TDFN-EP*
TDFNTOP VIEW
VCC
OUT1
SCL
FS3 (N.C.)
FS2 (N.C.)
*EXPOSED PAD
( ) INDICATES FOR DS4402 ONLY.
14OUT3 (N.C.)
OUT2 (N.C.)
SDA12GND9A0FS18OUT0FS0
DS4404/
DS4402
*EP
(3mm × 3mm × 0.8mm)
Pin Configuration
DS4402/DS4404wo/Four-Channel, I2C Adjustable Current DAC
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS(TA= -40°C to +85°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC, SDA, and SCL
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on A0, A1, FS0, FS1, FS2, FS3,
OUT0, OUT1, OUT2, and OUT3 Relative to
Ground................-0.5V to (VCC+ 0.5V) (Not to exceed 6.0V.)
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature.....................................Refer to IPC/JEDEC
J-STD-020 Specification
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Note 1) 2.7 5.5 V
Input Logic 1 (SDA, SCL, A0, A1) VIH 0.7 x VCC VCC + 0.3 V
Input Logic 0 (SDA, SCL, A0, A1) VIL -0.3 0.3 x VCC V
DC ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +5.5V, TA= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DS4402 500 Supply Current ICCVCC = 5.5V
(Note 2) DS4404 500 μA
Input Leakage (SDA, SCL) IIL VCC = 5.5V 1 μA
Output Leakage (SDA) IL 1 μA
VOL = 0.4V 3 Output Current Low (SDA) IOLVOL = 0.6V 6 mA
Address Input Resistors RIN240 k
Reference Voltage VREF 1.23 V
I/O Capacitance CI/O 10 pF
OUTPUT CURRENT CHARACTERISTICS(VCC= +2.7V to +5.5V, TA= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Voltage for Sinking Current VOUT:SINK (Note 3) 0.5 VCC V
Output Voltage for Sourcing
Current VOUT:SOURCE (Note 3) 0 VCC -
0.5 V
Full-Scale Sink Output Current IOUT:SINK (Note 3) 0.5 2.0 mA
Full-Scale Source Output Current IOUT:SOURCE (Note 3) -2.0 -0.5 mA
Output-Current Full-Scale
Accuracy IOUT:FS
+25°C, VCC = 4.0V; using ideal RFS
resistor; VOUT:SINK = 0.5V;
VOUT:SOURCE = VCC - 0.8V
2.5 5.0 %
Output-Current Temperature Drift IOUT:TC (Note 4) 70 ppm/°C
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
Note 1:All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2:Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven
to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current
including IRFSis ICC+ (2 x IRFS).
Note 3:The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4:Temperature drift excludes drift caused by external resistor.
Note 5:Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 31.
Note 6:Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 7:Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 8:CB—total capacitance of one bus line in pF.
OUTPUT CURRENT CHARACTERISTICS (continued)(VCC= +2.7V to +5.5V, TA= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output-Current Power-Supply
Rejection Ratio DC 0.33 %/V
Output Leakage Current at Zero
Current Setting IZERO -1 +1 μA
Output-Current Differential
Linearity DNL (Note 5) 0.5 LSB
Output-Current Integral Linearity INL (Note 6) 1 LSB
2C AC ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +5.5V, TA= -40°C to +85°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCL Clock FrequencyfSCL(Note 7)0400kHz
Bus Free Time Between STOP
and START ConditionstBUF1.3µs
Hold Time (Repeated) START
ConditiontHD:STA0.6µs
Low Period of SCLtLOW1.3µs
High Period of SCLtHIGH0.6µs
Data Hold TimetDH:DAT00.9µs
Data Setup TimetSU:DAT100ns
START Setup TimetSU:STA0.6µs
SDA and SCL Rise TimetR(Note 8)20 +
0.1CB300ns
SDA and SCL Fall TimetF(Note 8)20 +
0.1CB300ns
STOP Setup TimetSU:STO0.6µs
SDA and SCL Capacitive LoadingCB(Note 8)400pF
DS4402/DS4404wo/Four-Channel, I2C Adjustable Current DACVCC
VCC
RFS0RFS1RFS2RFS3
SDASCLA1A0
GND
FS0FS1OUT1OUT0
CURRENT
DAC0
F8h F9h
SOURCE OR
SINK MODE
FS2OUT2FS3OUT3
CURRENT
DAC3
31-POSITIONS
EACH FOR SINK
AND SOURCE
MODE
FAh FBh
DS4402/DS4404
DS4404
CURRENT
DAC1
CURRENT
DAC2
I2C-COMPATIBLE
SERIAL INTERFACE
Figure 1. Functional Diagram
Pin Description
PIN
DS4404DS4402
NAMEFUNCTION1 1 SDA I2C Serial Data. Input/output for I2C data.
2 2 SCL I2C Serial Clock. Input for I2C clock.
3 3 GND Ground
4 — FS3
5 — FS2
6 6 FS1
7 7 FS0
Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only
two inputs: FS0 and FS1.)
8 8 OUT0
10 10 OUT1
12 — OUT2
14 — OUT3
Current Output. Sinks or sources the current determined by the I2C interface and the
resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.)
9, 11 9, 11 A0, A1 Address Select Inputs. Tri-level inputs (VCC, GND, N.C.) determine the I2C slave address.
See the Detailed Description section for the nine available device addresses.
13 13 VCC Power Supply 4, 5, 12, 14 N.C. No Connection — EP Exposed Pad. Leave unconnected or connect to GND.
Detailed DescriptionThe DS4402/DS4404 contain two/four I2C adjustable
current sources (Figure 1) that are each capable of
sinking and sourcing current. Each output has 31 sink
and 31 source settings that are programmed through
the I2C interface. The full-scale ranges (and corre-
sponding step sizes) of the outputs are determined by
external resistors that adjust the output currents over a
4:1 range. The formula to determine the external resis-
tor values (RFS) for each of the outputs is given by:
Equation 1:RFS= (VREF/ IFS) x (31 / 4)
where IFS= desired full-scale current
On power-up, the DS4402/DS4404 output zero current.
This is done to prevent it from sinking or sourcing an
incorrect current before the system host controller has
had a chance to modify the device’s setting.
As a source for biasing instrumentation or other cir-
cuits, the DS4402/DS4404 provide a simple and inex-
pensive current source with an I2C interface for control.
The adjustable full-scale range allows the application to
get the most out of its 5-bit sink or source resolution.
When used in adjustable power-supply applications
(see the Typical Operating Circuit), the DS4402/DS4404
do not affect the initial power-up supply voltage because
it defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating point.
By using the external resistor to set the output current
range, the devices provide flexibility for adjusting the
impedances of the feedback network or the range over
which the power supply can be controlled or margined.
2C Slave AddressThe DS4402/DS4404 respond to one of nine I2C slave
addresses determined by the two tri-level address
inputs. The three input states are connected to VCC,
connected to ground, or disconnected. To sense the
disconnected state (Figure 2), the address inputs have
weak internal resistors that pull the pins to mid-supply.
Table 1 lists the slave address determined by the
address input combinations.
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
Table 1. Slave AddressesA0SLAVE ADDRESS
(HEXADECIMAL)GNDGND90h
GNDVCC92h
VCCGND94h
VCCVCC96h
N.C.GND98h
N.C.VCC9Ah
GNDN.C.9Ch
VCCN.C.9Eh
N.C.N.C.A0hI2C
ADDRESS
DECODE
RINRIN
VCC
RINRIN
Figure 2. I2C Address Inputs
DS4402/DS4404
Memory OrganizationTo control the DS4402/DS4404’s current sources, write
to the memory addresses listed in Table 2.
The format of each output control register is given by:
Where:
Example: IFS0= 800µA, and register F8h is written to a
value of 92h. Calculate the value of external resistance
required, and the magnitude of the output current with
this register setting.
RFS = (VREF/ 800µA) x (31 / 4) = 11.9kΩ
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 12h (18
decimal). The magnitude of the output current is equal to:
800µA x (18 / 31) = 465µA
2C Serial Interface Description2C DefinitionsThe following terminology is commonly used to describe
I2C data transfers:
Master Device:The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices:Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy:Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition:A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition:A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Repeated START Condition:The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition. See Figure 3 for applicable timing.
Bit Write:Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.
Bit Read:At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
wo/Four-Channel, I2C Adjustable Current DAC
MSBLSBSXXD4D3D2D1D0
BITNAMEFUNCTIONPOWER-ON
DEFAULTSign Bit
Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.ReservedReserved. Both bits read
zero.00bData
5-Bit Data Word Controlling
DAC Output. Setting 00000b
outputs zero current
regardless of the state of the
sign bit.
00000b
Table 2. Memory Addresses
MEMORY ADDRESS
(HEXADECIMAL)CURRENT SOURCEF8hOUT0
F9hOUT1
FAh*OUT2*
FBh*OUT3*
*Only for DS4404.
