DS34T101GN ,Single/Dual/Quad/Octal TDM-Over-Packet ChipPIN DESCRIPTIONS........28 9.1 SHORT
DS34T101GN+ ,Single/Dual/Quad/Octal TDM-Over-Packet ChipFEATURES ....20 8 OVERVIEW OF MAJOR OPERATIONAL MODES......25 8.1 INTERNAL MODE..25 8.1.1 Internal ..
DS34T102 ,Single/Dual/Quad/Octal TDM-Over-Packet ChipFeatures Full-Featured IC Includes E1/T1 LIUs and These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC Frame ..
DS34T108 ,Single/Dual/Quad/Octal TDM-Over-Packet ChipTable of Contents 1 INTRODUCTION .....10 2 ACRONYMS AND GLOSSARY10 3 APPLICABLE STANDARDS ....13 4 ..
DS34T108GN ,Single/Dual/Quad/Octal TDM-Over-Packet ChipFUNCTIONAL DESCRIPTION44 10.1 POWER-SUPPLY CONSIDERATIONS........44 10.2 CPU INTERFACE ........44 1 ..
DS34T108GN+ ,Single/Dual/Quad/Octal TDM-Over-Packet ChipApplications 10/100 Ethernet MAC Supports MII/RMII/SSMII TDM Circuit Extension Over PSN Selecta ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-24NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-3 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-3-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-3NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-3NUE-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS34T101GN-DS34T101GN+-DS34T102-DS34T108-DS34T108GN-DS34T108GN+
Single/Dual/Quad/Octal TDM-Over-Packet Chip
________________________________________________________Maxim Integrated Products 1 DS34T101, DS34T102, DS34T104, DS34T108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. With built-in full-
featured E1/T1 framers and LIUs. These ICs
encapsulate the TDM-over-packet solution from
analog E1/T1 signal to Ethernet MII while preserving
options to make use of TDM streams at key
intermediate points. The high level of integration
available with the DS34T10x devices minimizes cost,
board space, and time to market.
Applications TDM Circuit Extension Over PSN Leased-Line Services Over PSN TDM Over GPON/EPON TDM Over Cable TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Functional Diagram
Features
Full-Featured IC Includes E1/T1 LIUs and
Framers, TDMoP Engine, and 10/100 MAC
Transport of E1, T1, E3, T3 or STS-1 TDM or
Other CBR Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP AAL1, HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section 7.
Ordering Information
PART PORTSTEMP RANGE PIN-PACKAGEDS34T101GN 1 -40C to +85C 484 TEBGA
DS34T101GN+ 1 -40C to +85C 484 TEBGA
DS34T102GN 2 -40C to +85C 484 TEBGA
DS34T102GN+ 2 -40C to +85C 484 TEBGA
DS34T104GN 4 -40C to +85C 484 TEBGA
DS34T104GN+ 4 -40C to +85C 484 TEBGA
DS34T108GN 8 -40C to +85C 484 HSBGA
DS34T108GN+8 -40C to +85C 484 HSBGA
+Denotes lead(Pb)-free/RoHS-compliant package (explanation).
CPU
Bus
Octal
E1/T1/J1
Transceiver LIUs
Framers
Clock Inputs TDM
Access
BERT
& CAS
xMII
Buffer
Manager
Circuit
Emulation
Engine Clock
Adapters
10/100Ethernet
MAC E1/T1
Interfaces
SDRAM
Interface
DS34T108 19-4835; 8/09
____________________________________________________DS34T101, DS34T102, DS34T104, DS34T108
Table of Contents
1 INTRODUCTION...................................................................................................................................10
2 ACRONYMS AND GLOSSARY............................................................................................................10
3 APPLICABLE STANDARDS................................................................................................................13
4 DETAILED DESCRIPTION...................................................................................................................14
5 APPLICATION EXAMPLES.................................................................................................................16
6 BLOCK DIAGRAM................................................................................................................................18
7 FEATURES...........................................................................................................................................20
8 OVERVIEW OF MAJOR OPERATIONAL MODES..............................................................................25 8.1 INTERNAL MODE................................................................................................................................25
8.1.1 Internal One-Clock Mode...........................................................................................................................26
8.1.2 Internal Two-Clock Mode...........................................................................................................................26
8.2 EXTERNAL MODE..............................................................................................................................27
9 PIN DESCRIPTIONS.............................................................................................................................28 9.1 SHORT PIN DESCRIPTIONS................................................................................................................28
9.2 DETAILED PIN DESCRIPTIONS............................................................................................................30
10 FUNCTIONAL DESCRIPTION............................................................................................................44 10.1 POWER-SUPPLY CONSIDERATIONS..................................................................................................44
10.2 CPU INTERFACE.............................................................................................................................44
10.3 SPI INTERFACE...............................................................................................................................47
10.3.1 SPI Operation..........................................................................................................................................47
10.3.2 SPI Modes...............................................................................................................................................48
10.3.3 SPI Signals..............................................................................................................................................49
10.3.4 SPI Protocol.............................................................................................................................................49
10.4 CLOCK STRUCTURE.........................................................................................................................52
10.5 RESET AND POWER-DOWN..............................................................................................................53
10.6 TDM-OVER-PACKET BLOCK.............................................................................................................54
10.6.1 Packet Formats.......................................................................................................................................54
10.6.2 Typical Application...................................................................................................................................63
10.6.3 Clock Recovery.......................................................................................................................................65
10.6.4 Timeslot Assigner (TSA)..........................................................................................................................66
10.6.5 CAS Handler............................................................................................................................................67
10.6.6 AAL1 Payload Type Machine..................................................................................................................71
10.6.7 HDLC Payload Type Machine.................................................................................................................74
10.6.8 RAW Payload Type Machine..................................................................................................................75
10.6.9 SDRAM and SDRAM Controller..............................................................................................................79
10.6.10 Jitter Buffer Control (JBC).....................................................................................................................80
10.6.11 Queue Manager.....................................................................................................................................83
10.6.12 Ethernet MAC........................................................................................................................................95
10.6.13 Packet Classifier....................................................................................................................................98
10.6.14 Packet Trailer Support.........................................................................................................................101
10.6.15 Counters and Status Registers...........................................................................................................102
10.6.16 Connection Level Redundancy...........................................................................................................102
10.6.17 OAM Signaling.....................................................................................................................................103
10.7 GLOBAL RESOURCES....................................................................................................................104
____________________________________________________DS34T101, DS34T102, DS34T104, DS34T108 10.9.1 TDMoP Interrupts..................................................................................................................................104
10.9.2 LIU, Framer and BERT Interrupts.........................................................................................................106
10.10 ELASTIC STORES AND FRAMER SYSTEM INTERFACE.....................................................................108
10.10.1 Elastic Store Initialization.....................................................................................................................108
10.10.2 Minimum Delay Mode..........................................................................................................................109
10.10.3 Additional Elastic Store Information....................................................................................................109
10.11 FRAMERS....................................................................................................................................111
10.11.1 T1 and E1 Framing Formats...............................................................................................................111
10.11.2 T1 Transmit Frame Synchronizer........................................................................................................115
10.11.3 Signaling..............................................................................................................................................115
10.11.4 T1 Datalink..........................................................................................................................................118
10.11.5 E1 Datalink..........................................................................................................................................120
10.11.6 Maintenance and Alarms.....................................................................................................................121
10.11.7 E1 Automatic Alarm Generation..........................................................................................................123
10.11.8 Error Count Registers..........................................................................................................................124
10.11.9 DS0 Monitoring Function.....................................................................................................................125
10.11.10 Framer and Payload Loopbacks.......................................................................................................126
10.11.11 Per-Channel Loopback......................................................................................................................126
10.11.12 Per-Channel Idle Code Insertion.......................................................................................................126
10.11.13 Digital Milliwatt Code Generation......................................................................................................127
10.11.14 In-Band Loop Code Generation and Detection (T1 Only).................................................................127
10.11.15 G.706 Intermediate CRC-4 Recalculation (E1 Only).........................................................................128
10.11.16 SLC–96 Operation (T1 Only).............................................................................................................128
10.12 HDLC CONTROLLERS.................................................................................................................129
10.12.1 Receive HDLC Controller....................................................................................................................130
10.12.2 Transmit HDLC Controller...................................................................................................................132
10.13 LINE INTERFACE UNITS (LIU).......................................................................................................134
10.13.1 LIU Operation......................................................................................................................................135
10.13.2 LIU Transmitter....................................................................................................................................136
10.13.3 LIU Receiver........................................................................................................................................138
10.13.4 Jitter Attenuator...................................................................................................................................140
10.13.5 LIU Loopbacks.....................................................................................................................................141
10.14 BIT ERROR RATE TEST FUNCTIONS (BERTS)...............................................................................144
10.14.1 BERT General Description..................................................................................................................144
10.14.2 BERT Features....................................................................................................................................144
10.14.3 BERT Configuration and Monitoring....................................................................................................144
10.14.4 BERT Receive Pattern Detection........................................................................................................145
10.14.5 BERT Transmit Pattern Generation....................................................................................................147
10.15 LIU - FRAMER CONNECTIONS......................................................................................................148
11 DEVICE REGISTERS.......................................................................................................................149 11.1 ADDRESSING.................................................................................................................................149
11.2 TOP-LEVEL MEMORY MAP.............................................................................................................150
11.3 GLOBAL REGISTERS......................................................................................................................151
11.4 TDM-OVER-PACKET REGISTERS....................................................................................................159
11.4.1 Configuration and Status Registers.......................................................................................................160
11.4.2 Bundle Configuration Tables.................................................................................................................174
11.4.3 Counters................................................................................................................................................184
11.4.4 Status Tables.........................................................................................................................................187
11.4.5 Timeslot Assignment Tables.................................................................................................................189
11.4.6 CPU Queues.........................................................................................................................................191
11.4.7 Transmit Buffers Pool............................................................................................................................196
11.4.8 Jitter Buffer Control................................................................................................................................197
11.4.9 Transmit Software CAS.........................................................................................................................201
11.4.10 Receive Line CAS...............................................................................................................................203
____________________________________________________DS34T101, DS34T102, DS34T104, DS34T108 11.4.13 Receive SW CAS................................................................................................................................206
11.4.14 Interrupt Controller...............................................................................................................................207
11.4.15 Packet Classifier..................................................................................................................................213
11.4.16 Ethernet MAC......................................................................................................................................214
11.5 FRAMER, LIU AND BERT REGISTERS.............................................................................................224
11.5.1 Receive Framer Registers.....................................................................................................................224
11.5.2 Transmit Formatter Registers................................................................................................................272
11.5.3 LIU Registers.........................................................................................................................................303
11.5.4 BERT Registers.....................................................................................................................................312
12 JTAG INFORMATION.......................................................................................................................320
13 DC ELECTRICAL CHARACTERISTICS..........................................................................................325
14 AC TIMING CHARACTERISTICS.....................................................................................................326 14.1 LIU CHARACTERISTICS..................................................................................................................326
14.2 LIU AND FRAMER TDM INTERFACE TIMING.....................................................................................327
14.3 CPU INTERFACE TIMING................................................................................................................330
14.4 SPI INTERFACE TIMING..................................................................................................................331
14.5 SDRAM INTERFACE TIMING..........................................................................................................332
14.6 TDM-OVER-PACKET TDM INTERFACE TIMING................................................................................335
14.7 ETHERNET MII/RMII/SSMII INTERFACE TIMING..............................................................................338
14.8 CLAD AND SYSTEM CLOCK TIMING................................................................................................340
14.9 JTAG INTERFACE TIMING..............................................................................................................341
15 APPLICATIONS................................................................................................................................342 15.1 CONNECTING A SERIAL INTERFACE TRANSCEIVER..........................................................................342
15.2 CONNECTING AN ETHERNET PHY OR MAC....................................................................................343
15.3 IMPLEMENTING CLOCK RECOVERY IN HIGH SPEED APPLICATIONS..................................................345
15.4 CONNECTING A MOTOROLA MPC860 PROCESSOR........................................................................345
15.4.1 Connecting the Bus Signals..................................................................................................................345
15.4.2 Connecting the H_READY_N Signal.....................................................................................................348
15.5 WORKING IN SPI MODE.................................................................................................................349
15.6 CONNECTING SDRAM DEVICES....................................................................................................349
16 PIN ASSIGNMENT............................................................................................................................350 16.1 BOARD DESIGN FOR MULTIPLE DS34T10X DEVICES......................................................................350
16.2 DS34T101 PIN ASSIGNMENT........................................................................................................361
16.3 DS34T102 PIN ASSIGNMENT........................................................................................................362
16.4 DS34T104 PIN ASSIGNMENT........................................................................................................363
16.5 DS34T108 PIN ASSIGNMENT........................................................................................................364
17 PACKAGE INFORMATION..............................................................................................................365
18 THERMAL INFORMATION...............................................................................................................365
19 DATA SHEET REVISION HISTORY.................................................................................................366 ____________________________________________________DS34T101, DS34T102, DS34T104, DS34T108
List of Figures Figure 5-1. TDMoP in a Metropolitan Packet Switched Network..............................................................................16
Figure 5-2. TDMoP in Cellular Backhaul...................................................................................................................17
Figure 6-1. Top-Level Block Diagram........................................................................................................................18
Figure 6-2. TDM Cross-Connection Block Diagram..................................................................................................19
Figure 8-1. Internal Mode Block Diagram.................................................................................................................25
Figure 8-2. Internal One-Clock Mode.......................................................................................................................26
Figure 8-3. Internal Two Clock Mode (Framed)........................................................................................................27
Figure 8-4. Internal Two Clock Mode (Unframed)....................................................................................................27
Figure 10-1. CPU Interface Functional Diagram......................................................................................................44
Figure 10-2. Write Access, 32-Bit Bus......................................................................................................................45
Figure 10-3. Read Access, 32-Bit Bus......................................................................................................................46
Figure 10-4. Read/Write Access, 16-Bit Bus............................................................................................................46
Figure 10-5. Write Access to the SDRAM, 16-Bit Bus..............................................................................................47
Figure 10-6. Read Access to the SDRAM, 16-Bit Bus.............................................................................................47
Figure 10-7. SPI Interface with One Slave...............................................................................................................48
Figure 10-8. SPI Interface Timing, SPI_CP=0..........................................................................................................48
Figure 10-9. SPI Interface Timing, SPI_CP=1..........................................................................................................48
Figure 10-10. TDM-over-Packet Encapsulation Formats.........................................................................................55
Figure 10-11. Single VLAN Tag Format...................................................................................................................56
Figure 10-12. Stacked VLAN Tag Format................................................................................................................56
Figure 10-13. UDP/IPv4 Header Format..................................................................................................................56
Figure 10-14. UDP/IPv6 Header Format..................................................................................................................57
Figure 10-15. MPLS Header Format........................................................................................................................58
Figure 10-16. MEF Header Format...........................................................................................................................58
Figure 10-17. L2TPv3/IPv4 Header Format.............................................................................................................59
Figure 10-18. L2TPv3/IPv6 Header Format.............................................................................................................60
Figure 10-19. Control Word Format..........................................................................................................................60
Figure 10-20. RTP Header Format...........................................................................................................................61
Figure 10-21. VCCV OAM Packet Format................................................................................................................62
Figure 10-22. UDP/IP-Specific OAM Packet Format................................................................................................63
Figure 10-23. TDM Connectivity over a PSN...........................................................................................................64
Figure 10-24. TDMoP Packet Format in a Typical Application.................................................................................64
Figure 10-25. TDMoMPLS Packet Format in a Typical Application.........................................................................64
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction...........................................................................67
Figure 10-27. Transmit SW CAS Table Format for E1 and T1-ESF Interfaces........................................................68
Figure 10-28. Transmit SW CAS Table Format for T1-SF Interfaces......................................................................68
Figure 10-29. E1 MF Interface RSIG Timing Diagram (two_clocks=1)....................................................................68
Figure 10-30. T1 ESF Interface RSIG Timing Diagram (two_clocks=0)..................................................................69
Figure 10-31. T1 SF Interface RSIG (two_clocks=0) – Timing Diagram..................................................................69
Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction...........................................................................70
Figure 10-33. E1 MF Interface TSIG Timing Diagram..............................................................................................71
Figure 10-34. T1 ESF Interface TSIG Timing Diagram............................................................................................71
Figure 10-35. T1 SF Interface TSIG Timing Diagram...............................................................................................71
Figure 10-36. AAL1 Mapping, General.....................................................................................................................72
Figure 10-37. AAL1 Mapping, Structured-Without-CAS Bundles.............................................................................73
Figure 10-38. HDLC Mapping...................................................................................................................................74
Figure 10-39. SAToP Unstructured Packet Mapping...............................................................................................75
Figure 10-40. CESoPSN Structured-Without-CAS Mapping....................................................................................76
Figure 10-41. CESoPSN Structured-With-CAS Mapping (No Frag, E1 Example)...................................................76
Figure 10-42. CESoPSN Structured-With-CAS Mapping (No Frag, T1-ESF Example)...........................................77
Figure 10-43. CESoPSN Structured-With-CAS Mapping (No Frag, T1-SF Example).............................................77
Figure 10-44. CESoPSN Structured-With-CAS Mapping (Frag, E1 Example)........................................................78
Figure 10-45. SDRAM Access through the SDRAM Controller................................................................................80
