DS3170+ ,DS3/E3 Single-Chip TransceiverAPPLICATIONS Receive or Transmit Path Access Concentrators Multiservice Access Interfaces to 75 ..
DS3170DK ,DS3/E3 Single-Chip Transceiver Design Kit DS3170DK DS3/E3 Single-Chip Transceiver Design Kit
DS3170N ,DS3/E3 Single-Chip TransceiverFEATURES Single-Chip Transceiver for DS3 and E3 The DS3170 combines a DS3/E3 framer and an LIU ..
DS3170N+ ,DS3/E3 Single-Chip TransceiverFUNCTIONAL DESCRIPTION 53 10.1 PROCESSOR BUS INTERFACE ........ 53 10.1.1 SPI Serial Port Mode.. 53 ..
DS3171N+ ,Single/Dual/Triple/Quad DS3/E3 Single-Chip TransceiversFEATURES (CONTINUED) Devices and the DS316x Family of Devices Loopbacks Include Line, Diagnostic, ..
DS3172 ,3.3 V, single/dual/triple/quad DS3/E3 single-chip transceiverFEATURES (CONTINUED) Devices and the DS316x Family of Devices Loopbacks Include Line, Diagnostic ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3170+-DS3170N+
DS3/E3 Single-Chip Transceiver
GENERAL DESCRIPTION The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS Access Concentrators Multiservice Access
Platforms (MSAPs) Routers and Switches
SONET/SDH ADM Multiservice Protocol
Platform (MSPPs) SONET/SDH Muxes
PBXs Test Equipment
PDH Multiplexer/
Demultiplexer
Digital Cross Connect
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS3170 0°C to +70°C 100 CSBGA
DS3170+ 0°C to +70°C 100 CSBGA
DS3170N -40°C to +85°C 100 CSBGA
DS3170N+ -40°C to +85°C 100 CSBGA
+Denotes a lead(Pb)-free/RoHS compliant package.
FUNCTIONAL DIAGRAM
DS3170 DS3/E3 LINE
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES Single-Chip Transceiver for DS3 and E3 Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3 Jitter Attenuator can be Placed Either in the
Receive or Transmit Path Interfaces to 75 Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3) Uses 1:2 Transformers on Both Tx and Rx On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz Software Compatible with DS3171–DS3174 SCT
Product Family 8-/16-Bit Parallel and Slave SPI Serial (≤ 10Mbps)
Microprocessor Interface Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O) 100-Pin Small 11mm x 11mm (1mm) CSBGA Industrial Temperature Operation: -40°C to +85°C IEEE 1149.1 JTAG Test Port
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceiver 19-5785; Rev 2; 3/11
DS3170 DS3/E3 Single-Chip Transceiver
TABLE OF CONTENTS DETAILED DESCRIPTION 10 BLOCK DIAGRAMS 10 APPLICATIONS 12 FEATURE DETAILS 13 4.1 GLOBAL FEATURES .................................................................................................................................. 13
4.2 RECEIVE DS3/E3 LIU FEATURES .............................................................................................................. 13
4.3 JITTER ATTENUATOR FEATURES ................................................................................................................ 13
4.4 RECEIVE DS3/E3 FRAMER FEATURES ....................................................................................................... 13
4.5 TRANSMIT DS3/E3 FORMATTER FEATURES ................................................................................................ 14
4.6 TRANSMIT DS3/E3 LIU FEATURES ............................................................................................................ 14
4.7 CLOCK RATE ADAPTER FEATURES ............................................................................................................. 14
4.8 HDLC CONTROLLER FEATURES ................................................................................................................ 14
4.9 FEAC CONTROLLER FEATURES ................................................................................................................ 14
4.10 TRAIL TRACE BUFFER FEATURES .............................................................................................................. 15
4.11 BIT ERROR-RATE TESTER (BERT) FEATURES ............................................................................................ 15
4.12 LOOPBACK FEATURES .............................................................................................................................. 15
4.13 MICROPROCESSOR INTERFACE FEATURES ................................................................................................. 15
4.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................................. 15
4.15 TEST FEATURES ...................................................................................................................................... 15
STANDARDS COMPLIANCE 16 ACRONYMS AND GLOSSARY 17 MAJOR OPERATIONAL MODES 18 7.1 DS3/E3 FRAMED LIU MODE ..................................................................................................................... 18
7.2 DS3/E3 UNFRAMED LIU MODE ................................................................................................................. 20
7.3 DS3/E3 FRAMED POS/NEG MODE........................................................................................................... 21
7.4 DS3/E3 UNFRAMED POS/NEG MODE ...................................................................................................... 22
7.5 DS3/E3 FRAMED UNI MODE .................................................................................................................... 23
7.6 DS3/E3 UNFRAMED UNI MODE ................................................................................................................ 24
PIN DESCRIPTIONS 25 8.1 SHORT PIN DESCRIPTIONS........................................................................................................................ 25
8.2 DETAILED PIN DESCRIPTIONS .................................................................................................................... 27
8.3 PIN FUNCTIONAL TIMING ........................................................................................................................... 37
8.3.1 Line IO ............................................................................................................................................ 37
8.3.2 DS3/E3 Framing Overhead Functional Timing ................................................................................. 40
8.3.3 DS3/E3 Serial Data Interface .......................................................................................................... 41
8.3.4 Microprocessor Interface Functional Timing .................................................................................... 43
8.3.5 JTAG Functional Timing .................................................................................................................. 50
INITIALIZATION AND CONFIGURATION 51 9.1 MONITORING AND DEBUGGING .................................................................................................................. 52
10 FUNCTIONAL DESCRIPTION 53 10.1 PROCESSOR BUS INTERFACE .................................................................................................................... 53
10.1.1 SPI Serial Port Mode....................................................................................................................... 53
10.1.2 8/16 Bit Bus Widths ......................................................................................................................... 53
10.1.3 Ready Signal (RDY) ........................................................................................................................ 53
10.1.4 Byte Swap Modes ........................................................................................................................... 53
10.1.5 Read-Write/Data Strobe Modes....................................................................................................... 53
10.1.6 Clear on Read/Clear on Write Modes .............................................................................................. 53
10.1.7 Interrupt and Pin Modes .................................................................................................................. 54
10.1.8 Interrupt Structure ........................................................................................................................... 54
10.2 CLOCKS .................................................................................................................................................. 55
DS3170 DS3/E3 Single-Chip Transceiver
10.2.3 Line IO Pin Timing Source Selection ............................................................................................... 59
10.2.4 Clock Structures On Signal IO Pins ................................................................................................. 62
10.2.5 Gapped Clocks ............................................................................................................................... 63
10.3 RESET AND POWER-DOWN ....................................................................................................................... 63
10.4 GLOBAL RESOURCES ............................................................................................................................... 66
10.4.1 Clock Rate Adapter (CLAD) ............................................................................................................ 66
10.4.2 8 kHz Reference Generation ........................................................................................................... 66
10.4.3 One Second Reference Generation................................................................................................. 67
10.4.4 General-Purpose IO Pins ................................................................................................................ 68
10.4.5 Performance Monitor Counter Update Details ................................................................................. 69
10.4.6 Transmit Manual Error Insertion ...................................................................................................... 70
10.5 PORT RESOURCES ................................................................................................................................... 71
10.5.1 Loopbacks ...................................................................................................................................... 71
10.5.2 Loss Of Signal Propagation ............................................................................................................. 73
10.5.3 AIS Logic ........................................................................................................................................ 73
10.5.4 Loop Timing Mode .......................................................................................................................... 75
10.5.5 HDLC Overhead Controller ............................................................................................................. 75
10.5.6 Trail Trace ...................................................................................................................................... 75
10.5.7 BERT .............................................................................................................................................. 75
10.5.8 System Port Pins ............................................................................................................................ 76
10.5.9 Framing Modes ............................................................................................................................... 77
10.5.10 Line Interface Modes....................................................................................................................... 77
10.6 DS3/E3 FRAMER / FORMATTER ................................................................................................................. 79
10.6.1 General Description ........................................................................................................................ 79
10.6.2 Features ......................................................................................................................................... 79
10.6.3 Transmit Formatter ......................................................................................................................... 80
10.6.4 Receive Framer .............................................................................................................................. 80
10.6.5 C-bit DS3 Framer/Formatter ............................................................................................................ 84
10.6.6 M23 DS3 Framer/Formatter ............................................................................................................ 87
10.6.7 G.751 E3 Framer/Formatter ............................................................................................................ 89
10.6.8 G.832 E3 Framer/Formatter ............................................................................................................ 91
10.7 HDLC OVERHEAD CONTROLLER ............................................................................................................... 96
10.7.1 General Description ........................................................................................................................ 96
10.7.2 Features ......................................................................................................................................... 97
10.7.3 Transmit FIFO ................................................................................................................................. 97
10.7.4 Transmit HDLC Overhead Processor .............................................................................................. 98
10.7.5 Receive HDLC Overhead Processor ............................................................................................... 98
10.7.6 Receive FIFO.................................................................................................................................. 99
10.8 TRAIL TRACE CONTROLLER....................................................................................................................... 99
10.8.1 General Description ........................................................................................................................ 99
10.8.2 Features ....................................................................................................................................... 100
10.8.3 Functional Description ................................................................................................................... 100
10.8.4 Transmit Data Storage .................................................................................................................. 101
10.8.5 Transmit Trace ID Processor ......................................................................................................... 101
10.8.6 Transmit Trail Trace Processing .................................................................................................... 101
10.8.7 Receive Trace ID Processor.......................................................................................................... 101
10.8.8 Receive Trail Trace Processing ..................................................................................................... 101
10.8.9 Receive Data Storage ................................................................................................................... 102
10.9 FEAC CONTROLLER .............................................................................................................................. 102
10.9.1 General Description ...................................................................................................................... 102
10.9.2 Features ....................................................................................................................................... 103
10.9.3 Functional Description ................................................................................................................... 103
10.10 LINE ENCODER/DECODER ....................................................................................................................... 104
10.10.1 General Description ...................................................................................................................... 104
10.10.2 Features ....................................................................................................................................... 105
10.10.3 B3ZS/HDB3 Encoder .................................................................................................................... 105
DS3170 DS3/E3 Single-Chip Transceiver
10.11 BERT .................................................................................................................................................. 108
10.11.1 General Description ...................................................................................................................... 108
10.11.2 Features ....................................................................................................................................... 108
10.11.3 Configuration and Monitoring ........................................................................................................ 108
10.11.4 Receive Pattern Detection ............................................................................................................. 109
10.11.5 Transmit Pattern Generation ......................................................................................................... 111
10.12 LIU – LINE INTERFACE UNIT .................................................................................................................... 112
10.12.1 General Description ...................................................................................................................... 112
10.12.2 Features ....................................................................................................................................... 112
10.12.3 Detailed Description ...................................................................................................................... 112
10.12.4 Transmitter ................................................................................................................................... 113
10.12.5 Receiver ....................................................................................................................................... 114
11 OVERALL REGISTER MAP 117
12 REGISTER MAPS AND DESCRIPTIONS 119 12.1 REGISTERS BIT MAPS ............................................................................................................................ 119
12.1.1 Global Register Bit Map ................................................................................................................ 119
12.1.2 HDLC Register Bit Map ................................................................................................................. 121
12.1.3 T3 Register Bit Map ...................................................................................................................... 123
12.1.4 E3 G.751 Register Bit Map ............................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map ............................................................................................................ 125
12.2 GLOBAL REGISTERS ............................................................................................................................... 126
12.2.1 Register Bit Descriptions ............................................................................................................... 126
12.3 PORT REGISTER .................................................................................................................................... 133
12.3.1 Register Bit Descriptions ............................................................................................................... 133
12.4 BERT .................................................................................................................................................. 144
12.4.1 BERT Register Map ...................................................................................................................... 144
12.4.2 BERT Register Bit Descriptions ..................................................................................................... 144
12.5 B3ZS/HDB3 LINE ENCODER/DECODER ................................................................................................... 151
12.5.1 Transmit Side Line Encoder/Decoder Register Map ...................................................................... 151
12.5.2 Receive Side Line Encoder/Decoder Register Map ....................................................................... 152
12.6 HDLC .................................................................................................................................................. 156
12.6.1 HDLC Transmit Side Register Map................................................................................................ 156
12.6.2 HDLC Receive Side Register Map ................................................................................................ 159
12.7 FEAC CONTROLLER .............................................................................................................................. 163
12.7.1 FEAC Transmit Side Register Map ................................................................................................ 163
12.7.2 FEAC Receive Side Register Map ................................................................................................. 165
12.8 TRAIL TRACE ......................................................................................................................................... 168
12.8.1 Trail Trace Transmit Side .............................................................................................................. 168
12.8.2 Trail Trace Receive Side Register Map ......................................................................................... 169
12.9 DS3/E3 FRAMER ................................................................................................................................... 174
12.9.1 Transmit DS3 ................................................................................................................................ 174
12.9.2 Receive DS3 Register Map ........................................................................................................... 176
12.9.3 Transmit G.751 E3 ........................................................................................................................ 183
12.9.4 Receive G.751 E3 Register Map ................................................................................................... 186
12.9.5 Transmit G.832 E3 Register Map .................................................................................................. 191
12.9.6 Receive G.832 E3 Register Map ................................................................................................... 194
13 JTAG INFORMATION 202 13.1 JTAG DESCRIPTION............................................................................................................................... 202
13.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION .......................................................................... 203
13.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ................................................................................... 205
13.4 JTAG ID CODES ................................................................................................................................... 206
13.5 JTAG FUNCTIONAL TIMING ..................................................................................................................... 207
13.6 IO PINS ................................................................................................................................................ 207
14 PIN CONFIGURATIONS 208
DS3170 DS3/E3 Single-Chip Transceiver
16.1 FRAMER DATA PATH AC CHARACTERISTICS ............................................................................................. 215
16.2 OVERHEAD PORT AC CHARACTERISTICS.................................................................................................. 216
16.3 MICRO INTERFACE AC CHARACTERISTICS ................................................................................................ 217
16.3.1 SPI Bus Mode ............................................................................................................................... 217
16.3.2 Parallel Bus Mode ......................................................................................................................... 219
16.4 CLAD JITTER CHARACTERISTICS ............................................................................................................ 222
16.5 LIU INTERFACE AC CHARACTERISTICS..................................................................................................... 222
16.5.1 Waveform Templates .................................................................................................................... 222
16.5.2 LIU Input/Output Characteristics.................................................................................................... 225
16.6 JTAG INTERFACE AC CHARACTERISTICS ................................................................................................. 227
17 PACKAGE INFORMATION 228
18 THERMAL INFORMATION 229
19 REVISION HISTORY 230
