DS3160 Fast Delivery |IC PHOENIX CO.,LIMITED

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DS3160
JT 6312kbps Secondary-Rate Line Interface Unit and Framer/Formatter
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
FEATURESSingle-chip JT 6312kbps secondary-rate line
interface unit (LIU) and framer/formatterSupports G.704 and NTT J2 frame formatsTransmit and receive path-monitor outputsB8ZS encoder and decoderGenerates and detects alarmsIntegrated HDLC controller handles LAPD
messages without host interventionIntegrated BERT supports performance
monitoringSupports 8-bit or 16-bit control3.3V supply with 5V tolerant I/O; low-power
CMOSAvailable in 100-pin LQFP packageIEEE 1149.1 JTAG support
ORDERING INFORMATION
DS3160 100-pin LFQP 0°C to +70°C
DS3160C01 100-pin LFQP 0°C to +85°C
DS3160N 100-pin LFQP -40°C to +85°C
FUNCTIONAL DIAGRAM
APPLICATIONSRoutersSwitchesTest EquipmentAggregators/ConcentratorsPBXBase Stations
DESCRIPTION
The DS3160 device, which combines a line interface unit (LIU) with a formatter and framer, is compliant
with the JT 6312kbps secondary-rate user-network interface and supports the G.704 and NTT J2 frame
formats. A full-featured LIU with integrated jitter attenuator supports a software-programmable framer
and formatter. Framer features include alarm and error detection, on-chip HDLC controller for processing
of M-bit information, and programmable timeslot data-enable signal for 1.5Mbps, 3Mbps, 4.5Mbps, and
6Mbps frame formats. The formatter adds the required overhead to the user data and has the additional
capability of generating diagnostic errors. Loopback features, together with an on-chip bit-error-rate test
(BERT) function, allow easy isolation and monitoring of network segments.
DS3160
JT 6312kbps Secondary-Rate
Line Interface Unit
and Framer/Formatter
DS3160
1. MAIN FEATURES
Line Interface UnitIntegrated transmit and receive 6312kbps line interfaceRequires no special external components other than 1:1 transformersTransmit and receive signal-monitor outputsTransmit, receive, and monitor paths use the same transformer (1:1)Nominal pulse waveform: 2Vo-p ±0.3V, 50% pulse widthElectrical characteristics in accordance with TTC Standard JT-G703Adaptive receive equalizer adapts to coax cable loses from 0 to 15dBPerforms clock/data recovery and wave shapingTransmit line-driver monitoring checks for faulty transmitter or a shorted outputJitter attenuator that can be placed either in the receive path or the transmit path or disabledOn-board B8ZS coder/decoder with the option to be disabledAnalog and digital loopbacksAnalog loss of signal detectorTri-state-capable transmit and signal monitor line drivers for power management optionsCommercial temperature operating range: 0�C to +70�C
Framer/FormatterProvides frame synchronization and insertionFrame structure in accordance with TTC Standard JT-G704Frame alignment and cyclic redundancy check (CRC) in accordance with TTC Standard JT-G706Alarm detection and generationAIS and RAI generationSupports maintenance data link using an integrated HDLC controllerSupports generation of gapped receive and transmit clocks for interface to devices that only need
access to selected timeslotsProgrammable fractional circuit rates:
– TS1-24 (1.5Mbps)
– TS1-48 (3Mbps)
– TS1-72 (4.5Mbps)
– TS1-96 (6Mbps)
Path-Maintenance Data-Link HDLC ControllerDesigned to handle multiple LAPD messages without host intervention256-byte receive and transmit buffersHandles all of the normal Layer 2 tasks such as zero stuffing/destuffing, CRC generation/checking,
abort generation/checking, flag generation/detection, and byte alignmentProgrammable high and low watermarks for the FIFO
DS3160
BERTCan generate and detect the pseudorandom patterns of 27 - 1, 211 - 1, 215 - 1, and quasirandom signal
source (QRSS) as well as repetitive patterns from 1 to 32 bits in lengthLarge error counter (24 bits) allows testing to proceed for long periods without host interventionErrors can be inserted into the generated BERT patterns for diagnostic purposes
DiagnosticsDiagnostic loopbacks (transmit to receive)Line loopbacks (receive to transmit)Payload loopbackError counters for bipolar violations, code violations, loss of frame (LOF), framing bit errors, and
CRC errorsError counters can be either updated automatically on 1-second boundaries as timed by the DS3160,
or by software control, or by an external hardware pulseCan insert the bipolar violation errors and framing bit errorsInserted errors can be either controlled by software or by an external hardware pulseGenerates loss of frame
Control PortNonmultiplexed or multiplexed 16-bit control port (with an optional 8-bit mode)Intel and Motorola bus compatible
Packaging and Power3.3V low-power CMOS with 5V tolerant inputs and outputs100-pin LQFP packageIEEE 1149.1 JTAG test port
DS3160
Table 1A. APPLICABLE STANDARDS
1) Telecommunications Technique Council (TTC) JT-G.703, 1989 “Physical/Electrical Characteristics
of Hierarchical Digital Interfaces”
2) Telecommunications Technique Council (TTC) JT-G.704, 1989 “Synchronous Frame Structures
Used at Primary and Secondary Hierarchical Levels”
3) Telecommunications Technique Council (TTC) JT-G.706, 1989 “Frame Synchronization and CRC
Procedure”
4) International Telecommunication Union (ITU) G.703, April 1991 “Physical/Electrical Characteristics
of Hierarchical Digital Interfaces”
5) International Telecommunication Union (ITU) G.704, July 1995 “Synchronous Frame Structures
Used at 1544kbps, 6312kbps, 2048kbps, 8488kbps, and 44736kbps Hierarchical Levels”
6) International Telecommunication Union (ITU) G.775, November 1994 “Loss-of-Signal (LOS) and
Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
7) International Telecommunication Union (ITU) G.783, January 1994 “Characteristics of Synchronous
Digital Hierarchy (SDH) Equipment Functional Blocks”
8) International Telecommunication Union (ITU) O.151, October 1992 “Error Performance Measuring
Equipment Operating at the Primary Rate and Above”
9) International Telecommunication Union (ITU) O.153, October 1992 “Basic Parameters for the
Measurement of Error Performance at Bit Rates Below the Primary Rate”
10) International Telecommunication Union (ITU) O.161, 1984 “In-Service Code Violation Monitors for
Digital Systems”
DS3160
Figure 1A. BLOCK DIAGRAM
Rx+
Rx-
Tx+
Tx-
TxMON+
TxMON-
JTMS
JTDO
JTDI
JTCLK
CD0–CD15CA0–CA7CWR
(CRW)
CRD
(CDS)
CCSCIMCINTCMSTESTRSTCALE
RxMON+
RxMON-
FRSOF
FRCLK
FRD
FRDEN
FRLOF
FRLOS
FRMECU
FTCLK
FTD
FTDEN
FTSOF
FTMEI
MCLK
JTRST
DS3160
Figure 1B. LINE INTERFACE UNIT (LIU) BLOCK DIAGRAM
Rx+
Rx-
Tx+
TPOS
TCLK
TNEG
RNEG
RCLK
RPOS
MCLK
TxMON+
TxMON-
Tx-
RxMON+
RxMON-
DS3160
Figure 1C. FRAMER AND FORMATTER BLOCK DIAGRAM
FRSOF
FRCLK
FRD
FRDEN
RPOS
RNEG
RCLK
FRLOF
FRLOS
FRMECU
FTCLK
FTD
FTDEN
FTSOF
TPOS
TNEG
TCLK
FTMEI
DS3160
TABLE OF CONTENTS
1. MAIN FEATURES...................................................................................................................................2
2. SIGNAL DESCRIPTION.....................................................................................................................10
2.1 Overview/Signal Pin List......................................................................................................................10
2.2 CPU Bus Signal Description................................................................................................................15
2.3 Receive Framer Signal Description.......................................................................................................17
2.4 Transmit Formatter Signal Description..................................................................................................20
2.5 Receive LIU Signal Description............................................................................................................22
2.6 Transmit LIU Signal Description...........................................................................................................23
2.7 JTAG Signal Description......................................................................................................................24
2.8 Supply, Factory Test, and Reset Signal Descriptions.............................................................................25
3. MEMORY MAP AND REGISTER NOMENCLATURE..................................................................27
3.1 Memory Map......................................................................................................................................27
3.2 Register Description.............................................................................................................................28
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT............................................29
4.1 Master Reset and ID Register Descriptions..........................................................................................29
4.2 Master Configuration Registers Description..........................................................................................30
4.3 Master Status and Interrupt Register Descriptions.................................................................................35
5. FRAMER...............................................................................................................................................43
5.1 General Description..............................................................................................................................43
5.2 Framer Control Register Description.....................................................................................................44
5.3 Framer Status and Interrupt Register Descriptions................................................................................53
5.4 Performance Error Counters................................................................................................................59
6. BERT......................................................................................................................................................61
6.1 General Description.............................................................................................................................61
6.2 BERT Register Description..................................................................................................................61
7. HDLC CONTROLLER........................................................................................................................71
7.1 General Description.............................................................................................................................71
DS3160
7.3 HDLC Status and Interrupt Register Description..................................................................................77
8. LINE INTERFACE UNIT....................................................................................................................82
9. JTAG......................................................................................................................................................86
9.1 JTAG Description................................................................................................................................86
9.2 TAP Controller State Machine Description...........................................................................................87
9.3 Instruction Register and Instructions.....................................................................................................90
9.4 Test Registers......................................................................................................................................91
10. TEST REGISTERS.............................................................................................................................94
11. AC CHARACTERISTICS..................................................................................................................95
ABSOLUTE MAXIMUM RATINGS*..............................................................................................95
AC CHARACTERISTICS—FRAMER PORTS..............................................................................96
AC CHARACTERISTICS—CPU BUS............................................................................................98
AC CHARACTERISTICS—JTAG TEST PORT INTERFACE..................................................103
12. MECHANICAL DIMENSIONS......................................................................................................105
13. J2 FRAME FORMAT......................................................................................................................106
14. PROGRAMMING GUIDE AND OPERATIONAL NOTES........................................................107
14.1 Power-Up/Reset Discussion............................................................................................................107
DS3160
2. SIGNAL DESCRIPTION
2.1 Overview/Signal Pin List
This section describes the input and output signals on the DS3160. Signal names follow a convention that
is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and pin location.
Table 2.1A. SIGNAL NAMING CONVENTION
DS3160
Table 2.1B. SIGNAL DESCRIPTION/PIN LIST (PRELIMINARY PIN
ASSIGNMENT, SORTED BY PIN NUMBER)
DS3160
DS3160
Table 2.1C. SIGNAL DESCRIPTION/PIN LIST (PRELIMINARY PIN
ASSIGNMENT, SORTED BY SIGNAL)
DS3160
DS3160
2.2 CPU Bus Signal Description
Signal Name:CMS
Signal Description:CPU Bus Mode Select
Signal Type:Input
This signal should be connected low when the device is to be operated as a 16-bit bus. This signal should
be connected high when the device is to be operated as an 8-bit bus.
0 = CPU bus is in the 16-bit mode
1 = CPU bus is in the 8-bit mode
Signal Name:CIM
Signal Description:CPU Bus Intel/Motorola Bus Select
Signal Type:Input
The signal determines whether the CPU bus operates in the Intel mode (CIM = 0) or the Motorola mode
(CIM = 1). The signal names in parenthesis are operational when the device is in the Motorola mode.
0 = CPU bus is in the Intel mode
1 = CPU bus is in the Motorola mode
Signal Name:CD0 to CD15
Signal Description:CPU Bus Data Bus
Signal Type:Input/Output (Tri-State Capable)
The external host configures the device and obtains real-time status information about the device through
these signals. When reading data from the CPU bus, these signals are outputs. When writing data to the
CPU bus, these signals become inputs. When the CPU bus is operated in the 8-bit mode (CMS = 1), CD8
to CD15 are inactive and should be connected low.
Signal Name:CA0 to CA7
Signal Description:CPU Bus Address Bus
Signal Type:Input
These input signals determine which internal device configuration register that the external host wishes to
access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be
connected low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant
address bit.
Signal Name:CWR (CR/W)
Signal Description:CPU Bus Write Enable (CPU Bus Read/Write Select)
Signal Type:Input
In Intel mode (CIM = 0), this signal determines when data is to be written to the device. In Motorola
mode (CIM = 1), this signal is used to determine whether a read or write is to occur.
Signal Name:CRD (CDS)
Signal Description:CPU Bus Read Enable (CPU Bus Data Strobe)
Signal Type:Input
In Intel mode (CIM = 0), this signal determines when data is to be read from the device. In Motorola
mode (CIM = 1), a rising edge is used to write data into the device.
DS3160
Signal Name:CINT
Signal Description:CPU Bus Interrupt
Signal Type:Output
This output signal is driven low or open (float) during normal operation. It is driven low if one or more
unmasked interrupt sources within the device are active. The signal remains low until the interrupt is
either serviced or masked. This pin can be driven high in JTAG test modes.
Signal Name:CCS
Signal Description:CPU Bus Chip Select
Signal Type:Input
This active-low signal must be asserted for the device to accept a read or write command from an external
host.
Signal Name:CALE
Signal Description:CPU Bus Address Latch Enable
Signal Type:Input
This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
nonmultiplexed bus applications, CALE should be connected high. In multiplexed bus applications,
CA[7:0] should be connected to CD[7:0] and the falling edge of CALE latches the address.
DS3160
2.3 Receive Framer Signal Description
Signal Name:FRSOF
Signal Description:Receive Framer Start-of-Frame Sync Signal
Signal Type:Output
This signal pulses for one FRCLK period to indicate a frame or multiframe boundary. When configured in
the frame mode, FRSOF indicates the position of the first bit (bit position 1) in each J2 frame. When
configured in the multiframe mode, FRSOF indicates the position of the first bit (bit position 1) in each J2
multiframe. This signal can be configured to be either active high (normal mode) or active low (inverted
mode). See Figure 2.3B.
Signal Name:FRCLK
Signal Description:Receive Framer Clock
Signal Type:Output
This signal outputs the clock that is used to pass data through the receive framer. It can be sourced from
either the recovered receive clock, MCLK, or FTCLK inputs. During an LIU loss of signal (LIULOS = 1),
the clock applied at MCLK (or FTCLK if MCLK is connected high) appears at this signal. This signal is
used to clock the receive data out of the device at the FRD output. Data can be either updated on a rising
edge (normal mode) or a falling edge (inverted mode).
Signal Name:FRD
Signal Description:Receive Framer Serial Data
Signal Type:Output
This signal outputs data from the receive framer. This signal is updated either on the rising edge of
FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). In addition, this signal can be
internally inverted. FRD is forced to all 1’s during a LOS and/or LOF condition.
Signal Name:FRDEN
Signal Description:Receive Framer Serial Data-Enable or Gapped Clock Output
Signal Type:Output
This signal can be configured to either output a data enable or a gapped clock. In the data-enable mode,
this signal goes active when enabled timeslots are available at the FRD output and is inactive when
disabled timeslots or F-bits are being output at the FRD output. In the gapped clock mode, this signal
transitions for each bit contained in enabled timeslots and is suppressed for each bit of disabled timeslots
and the F-bits. This signal can be internally inverted (Figure 2.3A).
Signal Name:FRMECU
Signal Description:Receive Framer Manual Error-Counter Update Strobe
Signal Type:Input
The DS3160 can be configured to use this asynchronous input to initiate an updating of the internal error
counters. A 0-to-1 transition on this input causes the device to begin loading the internal error counters
with the latest error counts. This signal must be returned low before a subsequent updating of the error
counters can occur. The host must wait at least 100ns before reading the error counters to allow the device
time to update the error counters.
DS3160
Signal Name:FRLOS
Signal Description:Receive Framer Loss of Signal
Signal Type:Output
This signal is forced high when the receive framer is in a loss-of-signal (LOS) state. It remains high as
long as the LOS state persists and returns low when the framer exits the LOS state.
Signal Name:FRLOF
Signal Description:Receive Framer Loss of Frame
Signal Type:Output
This signal is forced high when the receive framer is in a loss-of-frame (LOF) state. It remains high as
long as the LOF state persists and returns low when the framer synchronizes.
Figure 2.3A. RECEIVE FRAMER TIMING
NOTES:
1) FRCLK, FRD, and FRDEN can be inverted by Master Configuration Register 2 (MC2).
2) Valid last active timeslots include TS24, TS48, TS72, and TS96.
FRCLK
INVERTED MODE
FRD
(NOTE 1)
FRCLK
NORMAL MODE
FRDENDATA STROBE MODE(NOTE 1)
FRDENGAPPED CLOCK MODE
(NOTE 1)
FIRST BIT OF THE
LAST BIT OF FRAMING
OVERHEAD, BIT 789
DS3160
Figure 2.3B. RECEIVE FRAMER TIMING
NOTES:
1) FRCLK, FRD, and FRSOF can be inverted by Master Configuration Register 2 (MC2).
FRCLKINVERTED MODE
FRD
(SEE NOTE)
FRCLKNORMAL MODE
FRSOF
(SEE NOTE)
FIRST BIT OF
FRAME, BIT 1
LAST BIT OF THE
FRAME, BIT 789
DS3160
2.4 Transmit Formatter Signal Description
Signal Name:FTSOF
Signal Description:Transmit Formatter Start-of-Frame Sync Signal
Signal Type:Output/Input (with internal 10kΩ pullup)
This signal can be configured to be either an input or output. When FTSOF is an input (default state), a
1-to-0 transition sets the first framing bit in each frame or multiframe. When FTSOF is an input, a pulse is
not required at every frame or multiframe boundary. The FTSOF as an input must not be less than a frame
cycle of 125µs, or must be configured as an output. When this signal is an output, it pulses for one
FTCLK period to indicate frame or multiframe boundary. When configured as an output and in the frame
mode, FTSOF pulses high for one out of every 789 clock cycles, providing a frame reference. When
configured as an output and in the multiframe mode, FTSOF pulses high for one out of every 3156 clock
cycles, providing a multiframe reference. This signal can be configured to be either active high (normal
mode) or active low (inverted mode) (Figure 2.4B).
Signal Name:FTCLK
Signal Description:Transmit Formatter Clock
Signal Type:Input
An accurate 6.312MHz �30ppm clock should be applied at this signal. This signal is used to clock data
into the transmit formatter. Transmit data can be clocked into the device either on a rising edge (normal
mode) or a falling edge (inverted mode).
Signal Name:FTD
Signal Description:Transmit Formatter Serial Data
Signal Type:Input
This signal inputs data into the transmit formatter. This signal can be sampled either on the rising edge of
FTCLK (normal mode) or the falling edge of FTCLK (inverted mode). In addition, the data input to this
signal can be internally inverted.
Signal Name:FTDEN
Signal Description:Transmit Formatter Serial Data-Enable or Gapped Clock Output
Signal Type:Output
This signal can be configured to either output a data enable or a gapped clock and use FTSOF for an
alignment reference or ignore FTSOF (free-running option, see ALTFTDEN in MC2). When using
FTSOF as a reference and in the data enable mode, this signal goes active when data should be made
available at the FTD input. When using FTSOF as a reference and in the gapped clock mode, this signal
acts as a demand clock for the FTD input and it transitions for each bit of data needed at the FTD input
and it is suppressed when the transmit formatter inserts overhead data and, therefore, no data is needed at
the FTD input. When the free-running mode is enabled, there is no correlation of FTDEN and when data
is made available at FTD. This signal can be internally inverted (Figure 2.4A).
Signal Name:FTMEI
Signal Description:Transmit Formatter Manual Error Insert Strobe
Signal Type:Input
The DS3160 can be configured to use this asynchronous input to cause errors to be inserted into the
transmitted data stream. A 0-to-1 transition on this input causes the device to begin the process of causing
errors to be inserted. This signal must be returned low before any subsequent errors can be generated. If
DS3160
Figure 2.4A. TRANSMIT FORMATTER TIMING
NOTES:
1) FTCLK, FTD, and FTDEN can be inverted by Master Configuration Register 2 (MC2).
2) Valid last active timeslots include TS24, TS48, TS72, and TS96.
Figure 2.4B. TRANSMIT FORMATTER TIMING
NOTES:
1) FTD and FTSOF can be inverted by Master Configuration Register 2 (MC2).
FTCLKINVERTED MODE
FTD
(NOTE 1)
FTCLK
NORMAL MODE
FTDEN
DATA STROBE MODE
(NOTE 1)
FTDEN
GAPPED CLOCK MODE(NOTE 1)
FIRST BIT OF THEFRAME, BIT 1LAST BIT OF FRAMING
OVERHEAD, BIT 789
FTCLK
INVERTED MODE
FTD
(SEE NOTE)
FTSOF
INPUT MODE
(SEE NOTE)
FTCLK
NORMAL MODE
FTSOF
OUTPUT MODE
(SEE NOTE)
DS3160
2.5 Receive LIU Signal Description
Signal Name:MCLK
Signal Description:Master Clock
Signal Type:Input
The clock input at this signal is used by the clock-and-data recovery machine. A 6.312MHz �30ppm
clock should be applied at this signal. The DS3160 requires a clock signal to always be present at MCLK
for correct device operation.
Signal Name:Rx+
Signal Description:Receive Analog Input
Signal Type:Input
This analog signal is coupled from the user-network interface by a 1:1 transformer.
Signal Name:Rx-
Signal Description:Receive Analog Input
Signal Type:Input
This analog signal is coupled from the user-network interface by a 1:1 transformer.
Signal Name:RxMON+
Signal Description:Receive Monitor Analog Output
Signal Type:Output
This analog output drives the receive monitor port by a 1:1 transformer.
Signal Name:RxMON-
Signal Description:Receive Monitor Analog Output
Signal Type:Output
This analog output drives the receive monitor port by a 1:1 transformer.
DS3160
2.6 Transmit LIU Signal Description
Signal Name:Tx+
Signal Description:Transmit Analog Output
Signal Type:Output
This analog output drives the user-network interface by a 1:1 transformer (Figure 8A).
Signal Name:Tx-
Signal Description:Transmit Analog Output
Signal Type:Output
This analog output drives the user-network interface by a 1:1 transformer (Figure 8A).
Signal Name:TxMON+
Signal Description:Transmit Monitor Analog Output
Signal Type:Output
This analog output drives the transmit monitor port by a 1:1 transformer (Figure 8A).
Signal Name:TxMON-
Signal Description:Transmit Monitor Analog Output
Signal Type:Output
This analog output drives the transmit monitor port by a 1:1 transformer (Figure 8A).
DS3160
2.7 JTAG Signal Description
Signal Name:JTCLK
Signal Description:JTAG IEEE 1149.1 Test Serial Clock
Signal Type:Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name:JTDI
Signal Description:JTAG IEEE 1149.1 Test Serial Data Input
Signal Type:Input (with internal 10kΩ pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be left open-circuited.
Signal Name:JTDO
Signal Description:JTAG IEEE 1149.1 Test Serial Data Output
Signal Type:Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open-circuited.
Signal Name:JTRST
Signal Description:JTAG IEEE 1149.1 Test Reset
Signal Type:Input (with internal 10kΩ pullup)
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be
set low and then high. This action sets the device into the boundary-scan bypass mode allowing normal
device operation. If boundary scan is not used, this signal should be held low.
Signal Name:JTMS
Signal Description:JTAG IEEE 1149.1 Test Mode Select
Signal Type:Input (with internal 10kΩ pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be left open-circuited.
DS3160
2.8 Supply, Factory Test, and Reset Signal Descriptions
Signal Name:RST
Signal Description:Global Hardware Reset
Signal Type:Input (with internal 10kΩ pullup)
This active-low asynchronous signal causes the device to be reset. When this signal is forced low, it
causes all of the internal registers to be forced to their default states. The device is held in a reset state as
long as this signal is low. This signal should be activated after the clocks MCLK and FTCLK are valid,
and must be returned high before the device can be configured for operation.
Signal Name:HIZ
Signal Description:Tri-State All Output Pins Enable
Signal Type:Input (with internal 10kΩ pullup)
This input should be left open-circuited by the user.
Signal Name:TEST, TENA1, TENA2
Signal Description:Factory Test Enable
Signal Type:Input (with internal 10kΩ pullup)
These inputs should be left open-circuited by the user.
Signal Names:LCLKI, LPOSI, LNEGI, DCLKI, DPOSI, DNEGI
Signal Description:Factory Test Signal
Signal Type:Input (with internal 10kΩ pullup)
These inputs should be left open-circuited by the user.
Signal Names:LCLKO, LPOSO, LNEGO, DCLKO, DPOSO, DNEGO
Signal Description:Factory Test Signal
Signal Type:Output
These outputs should be left open-circuited by the user.
Signal Names:TESTIO1, TESTIO2
Signal Description:Factory Test Signal
Signal Type:Input/Output (tri-state capable)
These signals should be left open-circuited by the user.
Signal Name:DVDD
Signal Description:Digital Positive Supply
Signal Type:N/A
3.3V (±5%). All DVDD signals should be connected together.
Signal Name:DVSS
Signal Description:Digital Ground Reference
Signal Type:N/A
All DVSS signals should be connected together.
DS3160
Signal Name:AVDD
Signal Description:Analog Positive Supply
Signal Type:N/A
3.3V (±5%). All AVDD signals should be connected together.
Signal Name:AVSS
Signal Description:Analog Ground Reference
Signal Type:N/A
All AVSS signals should be connected together.
DS3160
3. MEMORY MAP AND REGISTER NOMENCLATURE
3.1 Memory Map
Note: Address banks 5x, 6x, 7x, 8x, 9x, Ax, Bx, Cx, Dx, Ex, and Fx are not assigned.
DS3160
3.2 Register Description
The DS3160 register set consists of configuration registers and status registers. Configuration registers are
read-write except where noted as read-only; status registers are read-only. In this data sheet, registers are
described using the following descriptors:
Table 3.2A. REGISTER DESCRIPTION LABEL DEFINITIONS
NOTES:
1) The DS3160 ignores data written to bit locations with the name of “N/A.”
2) Reading bit locations with the name of “N/A” returns the value of zero.
3) Writing into read-only bit locations does not affect device operation.
DS3160
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 Master Reset and ID Register Descriptions
The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set
to 1, all of the internal registers are placed into their default state. A reset can also be invoked by the RST
hardware signal.
The upper byte of the MRID register is read-only and can be read by the host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:MRID
Register Description:Master Reset and ID Register
Register Address:00h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Master Software Reset (RST). When this bit is set to a 1 by the host, it forces all of the internal
registers to their default states. This bit must be set high for a minimum of 100ns. This software bit is
logically OR’ed with the hardware signal RST.
0 = normal operation
1 = force all internal registers to their default values
Bits 8 to 15/Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the
meaning of the ID bits. MRID bits 15 (MSB) to 8 (LSB) are a binary coded hexidecimal number that
represents the die revision according to the product top brand. Example: 10100010 = A2.Contact factory.
DS3160
4.2 Master Configuration Registers Description
Register Name:MC1Register Description:Master Configuration Register 1
Register Address:02h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Zero Code Suppression Disable (ZCSD)
0 = enable the B8ZS
1 = disable the B8ZS
Bit 1/Automatic One-Second Error Counters Update Defeat (AECU). When this bit is set low, the
device automatically updates the performance error counters on an internally created 1-second boundary.
The host is notified of the update by the setting of the OST status bit in the master status register. In this
mode, the host has a full 1-second period to retrieve the error information before it is overwritten with the
next update. When this bit is set high, the device defeats the automatic 1-second update and enables a
manual update mode. In the manual update mode, the device relies on either the framer manual error-
counter update (FRMECU) hardware-input signal or the MECU control bit to update the error counters.
The FRMECU hardware input signal and MECU control bit are logically OR’ed and hence a 0-to-1
transition on either initiates an error-counter update to occur. After either the FRMECU signal or MECU
bit has toggled, the host must wait at least 100ns before reading the error counters to allow the device
time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
Bit 2/Manual Error-Counter Update (MECU). A 0-to-1 transition on this bit causes the device to
update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit
must be cleared and set again for a subsequent update. This bit is logically OR’ed with the external
FRMECU hardware input signal. After this bit has toggled, the host must wait at least 100ns before
reading the error counters to allow the device time to complete the update.
Bit 3/Loss-of-Transmit Clock Mux Control (LOTCMC). The DS3160 can detect if the FTCLK fails to
transition. If this bit is set low, the device takes no action (other than setting the LOTC status bit) when
the FTCLK fails to transition. When this bit is set high, the device automatically switches to the internal
receive clock (RCLK) when the FTCLK fails and transmit AIS.
0 = do not switch to the RCLK signal if FTCLK fails to transition
1 = automatically switch to the RCLK signal if the FTCLK fails to transition and send AIS
DS3160
Bit 4/Transmit Alarm Indication Signal (TAIS). When this bit is set high, the transmitter generates an
unframed all 1’s. When this bit it set low, normal data is transmitted.
0 = do not transmit AIS
1 = transmit AIS
Bit 5/Data Enable Mode Select (DENMS). When this bit is set low, the FRDEN and FTDEN outputs
are asserted during enabled timeslots and deasserted during the disabled timeslots and F-bits of the frame.
When this bit is high, FRDEN and FTDEN are gapped clocks that pulse only during the enabled timeslots
of the frame.
0 = FRDEN and FTDEN are data enables
1 = FRDEN and FTDEN are gapped clocks
Bit 6/Diagnostic Loopback Enable (DLB). See Figures 1A and 1B for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 7/Line Loopback Enable (LLB). See Figures 1A and 1B for a visual description of this loopback.
0 = disable loopback
1 = enable loopback
Bit 8/Transmit Driver Output Enable (TDRVEN). When this bit is set low, the Tx+ and Tx- analog
outputs are tri-stated. When this bit is high, the Tx+ and Tx- analog outputs are enabled.
0 = Tx+ and Tx- outputs tri-stated
1 = Tx+ and Tx- outputs enabled
Bit 9/Transmit Monitor Output Enable (TMONEN). When this bit is set low, the TxMON+ and
TxMON- analog outputs are tri-stated. When this bit is high, the TxMON+ and TxMON- analog outputs
are enabled.
0 = TxMON+ and TxMON- outputs tri-stated
1 = TxMON+ and TxMON- outputs enabled
Bit 10/Receive Monitor Output Enable (RMONEN). When this bit is set low, the RxMON+ and
RxMON- analog outputs are tri-stated. When this bit is high, the RxMON+ and RxMON- analog outputs
are enabled.
0 = RxMON+ and RxMON- outputs tri-stated
1 = RxMON+ and RxMON- outputs enabled
Bit 11/Jitter Attenuator Enable (JAEN). When this bit is set low, the jitter attenuator is disabled. When
this bit is high, the jitter attenuator is enabled.
0 = jitter attenuator disabled
1 = jitter attenuator enabled
Bit 12/Jitter Attenuator Path Select (JASEL). When this bit is set low, the jitter attenuator is enabled in
the receive path. When this bit is high, the jitter attenuator is enabled in the transmit path.
0 = jitter attenuator in receive path
DS3160
Bit 13/Analog Loopback Enable (ALB). The analog loopback loops the transmit data (Tx+ and Tx-
outputs) directly back to the receive side (Rx+ and Rx- inputs). When this loopback is enabled, the data
output from the formatter continues to pass through the device, but the incoming receive data is replaced
with the data being output from the device. See the block diagrams in Section 1 for a visual description of
this loopback.
0 = disable loopback
1 = enable loopback
Bit 15/FRD AIS ENABLE (FRDAIS). When this bit is set high, receive data output at the FRD pin is
forced to all 1’s. When this bit is low, FRD operates normally.
0 = FRD operates normally
1 = data output at the FRD pin is forced to all 1’s
DS3160
Register Name:MC2
Register Description:Master Configuration Register 2
Register Address:04h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/FTDEN Invert Enable (FTDENI)
0 = do not invert the FTDEN signal (normal mode)
1 = invert the FTDEN signal (inverted mode)
Bit 1/FTD Invert Enable (FTDI)
0 = do not invert the FTD signal (normal mode)
1 = invert the FTD signal (inverted mode)
Bit 2/FTCLK Invert Enable (FTCLKI)
0 = do not invert the FTCLK signal (normal mode)
1 = invert the FTCLK signal (inverted mode)
Bit 3/FTSOF Invert Enable (FTSOFI)
0 = do not invert the FTSOF signal (normal mode)
1 = invert the FTSOF signal (inverted mode)
Bit 4/FTMEI Invert Enable (FTMEII)
0 = do not invert the FTMEI signal (normal mode)
1 = invert the FTMEI signal (inverted mode)
Bit 5/FRDEN Invert Enable (FRDENI)0 = do not invert the FRDEN signal (normal mode)
1 = invert the FRDEN signal (inverted mode)
Bit 6/FRD Invert Enable (FRDI)
0 = do not invert the FRD signal (normal mode)
1 = invert the FRD signal (inverted mode)
Bit 7/FRCLK Invert Enable (FRCLKI)
0 = do not invert the FRCLK signal (normal mode)
1 = invert the FRCLK signal (inverted mode)
DS3160
0 = do not invert the FRSOF signal (normal mode)
1 = invert the FRSOF signal (inverted mode)
Bit 9 / FRLOS Invert Enable (FRLOSI)
0 = do not invert the FRLOS signal (normal mode)
1 = invert the FRLOS signal (inverted mode)
Bit 10/FRLOF Invert Enable (FRLOFI)
0 = do not invert the FRLOF signal (normal mode)
1 = invert the FRLOF signal (inverted mode)
Bit 11/FRMECU Invert Enable (FRMECUI)
0 = do not invert the FRMECU signal (normal mode)
1 = invert the FRMECU signal (inverted mode)
Bit 12/Transmit Frame Sync I/O Control (FTSOFC). When this bit is set low, the FTSOF signal is an
input and the DS3160 uses it to determine the frame or multiframe boundaries. When this bit is high, the
FTSOF signal is an output and pulses for one FTCLK cycle at the beginning of each frame or multiframe.
0 = FTSOF is an input
1 = FTSOF is an output
Bit 13/Transmit Multiframe Enable (FTSOFM). When FTSOF is configured as an output, this bit
determines whether the FTSOF signal indicates frame or multiframe boundaries
0 = FTSOF output indicates frame boundaries
1 = FTSOF output indicates multiframe boundaries
Bit 14/Receive Multiframe Indication Enable (FRSOFM). This bit is used to control whether the
FRSOF output indicates frame or multiframe boundaries
0 = FRSOF indicates frame boundaries
1 = FRSOF indicates multiframe boundaries
Bit 15/Alternate Transmit Data Enable (ALTFTDEN). When set low, the FTDEN circuitry uses the
FTSOF signal to determine the start of the FTDEN signal (bit 1 of the FTDEN frame). When set high,
FTDEN is free-running and ignores FTSOF.
0 = use FTSOF to determine FTDEN start
1 = FTDEN free-running, ignores FTSOF
DS3160
4.3 Master Status and Interrupt Register Descriptions
Status Registers
The status registers in the DS3160 allow the host to monitor the real-time condition of the device. Most of
the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits within
the device are latched to ensure that the host can detect changes in state and the true status of the device.
There are three types of status bits in the DS3160. The first type is called an event status bit, which is
derived from a momentary condition or state that occurs within the device. The event status bits are
always cleared when read and can generate an interrupt when they are asserted. An example of an event
status bit is the one-second-timer boundary occurrence (OST).
The second type of status bit is called an alarm status bit, which is derived from conditions that can occur
for longer than an instance. The alarm status bits are cleared when read unless the alarm is still present.
The alarm status bits generate interrupts on a change in state in the alarm (i.e., when it is asserted or de-
asserted). An example of an alarm status bit is the loss of frame (LOF).
The third type of status bit is called a real-time status bit. The real-time status bit remains active as long as
the condition exists and generates an interrupt as long as the condition exists. An example of a real-time
status bit is the loss-of-transmit clock (LOTC).
DS3160
Figure 4.3A. EVENT STATUS BIT
Figure 4.3B. ALARM STATUS BIT
Figure 4.3C. REAL-TIME STATUS BIT
INTERNAL SIGNAL
STATUS BIT
INTERRUPT
READ
INTERNAL SIGNAL
STATUS BIT
INTERRUPT
READ
INTERNAL SIGNAL
STATUS BIT
INTERRUPT
READ
DS3160
Master Status Register (MSR)
The master status register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3160. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt-driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:MSR
Register Description:Master Status Register
Register Address:06h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/One-Second-Timer Boundary Occurrence (OST). This latched read-only event status bit is set to
a 1 on each 1-second boundary as timed by the DS3160. The device chooses an arbitrary 1-second
boundary that is timed from the RCLK signal. This bit is cleared when read and is not be set again until
another 1-second boundary has occurred. The setting of this status bit can cause a hardware interrupt to
occur if the OST bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed
to clear when this bit is read.
Bit 1/Counter Overflow Event (COVF). This latched read-only event status bit is set to a 1 if any of the
error counters saturate (the error counters saturate when full). This bit is cleared when read even if one or
more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to
occur if the COVF bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed
to clear when this bit is read.
Bit 2/Change in BERT Status (BERT). This read-only event status bit is set to a 1 if there is a major
change of status in the BERT receiver. A major change of status is defined as either a change in the
receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the bit counter or the error counter. The host must
read the status bits of the BERT in the BERT status register (BERTEC0) to determine the change of state.
This bit is cleared when read and is not set again until the BERT has experienced another change of state.
The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in the interrupt mask
for MSR (IMSR) register is set to a 1 (Figure 4.3D).
Bit 3/Change in HDLC Status (HDLC). This read-only event status bit is set to a 1 if there is a change
DS3160
a hardware interrupt to occur if the HDLC bit in the interrupt mask (IMSR) register is set to a 1 (Figure
4.3E).
Bit 4/Change in Framer Status (SR1). This read-only event-status bit is set to a 1 if there is a change of
status in the framer or formatter. The host must read the contents of SR1 to determine the change of state.
This bit is cleared when read and is not set again until the framer or formatter has experienced another
change of state. The setting of this status bit can cause a hardware interrupt to occur if the SR1 bit in the
interrupt mask (IMSR) register is set to a 1 (Figure 4.3F).
Bit 8/Loss-of-Transmit Clock Detected (LOTC). This latched read-only alarm status bit is set to a 1
when the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit is cleared
when a clock is detected at the FTCLK input. The setting of this status bit can cause a hardware interrupt
to occur if the LOTC bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is
allowed to clear when the device detects a clock at FTCLK. On reset, the LOTC status bit is set and then
immediately cleared if the clock is present.
Bit 10/Analog Loss-of-Signal Detected (LIULOS). This latched read-only alarm status bit is set to a 1
when the device detects that the incoming signal has dropped below -20dB of the nominal signal level.
When set, the recovered data is squelched and all 0’s are output to the framer. The analog loss-of-signal
detector is not clear until the signal level is above -16dB of the nominal signal level. Setting this status bit
can cause a hardware interrupt to occur if the LIULOS bit in the interrupt mask for MSR (IMSR) register
is set to a 1.
Bit 11/Transmit Driver Monitor (TXDRVR). This latched read-only alarm status bit is set to a 1 when
the analog-transmit outputs (Tx+ and Tx-) fail. The setting of this status bit can cause a hardware
interrupt to occur if the TXDRVR bit in the interrupt mask for MSR (IMSR) register is set to a 1.
DS3160
Figure 4.3D. BERT STATUS BIT FLOW
RLOS
(BERTEC0
BIT 4)
INTERNAL
RLOS SIGNAL
FROM BERT
INTERNAL
BIT ERROR
DETECTED
SIGNAL
FROM BERT
INTERNAL
COUNTER
OVERFLOW
SIGNAL FROM
BERT
BED
BECO OR BBCO
INT
HARDWARE
SIGNAL
BERT
STATUS BIT
(MSR BIT 2)
IESYNC (BERTC0 BIT 15)
IEBED (BERTC0 BIT 14)
IEOF (BERTC0 BIT 13)
BERT STATUS REGISTERMASTER STATUS REGISTER
EVENT LATCH CLEAR ON MSR READ
DS3160
Figure 4.3E. HDLC STATUS BIT FLOW
INTERNAL
TRANSMIT
LOW
WATERMARK
SIGNAL FROM
HDLC
INTERNAL
RECEIVE HIGH
WATERMARK
SIGNAL FROM
HDLC
INTERNAL
RECEIVE
PACKET START
SIGNAL FROM
HDLC
RHWM
RPS
HARDWARE
SIGNAL
HDLCSTATUS BIT
(MSR BIT 3)
RHWM (IHSR BIT 4)
RPS (IHSR BIT 5)RPE
INTERNAL
RECEIVE
PACKET END
SIGNAL FROM
HDLC
INTERNAL
TRANSMIT
FIFO
UNDERRUN
SIGNAL FROM
HDLCINTERNAL
RECEIVE
FIFO
OVERRUN
SIGNAL
FROM HDLC
ROVR
RPE (IHSR BIT 6)
TUDR (IHSR BIT 3)
ROVR (IHSR BIT 13)INTERNAL
RECEIVE
DETECT
SIGNAL
FROM HDLC
RABT
RABT (IHSR BIT 15)TRANSMIT
PACKET END
SIGNAL FROM
HDLC
TEND
TEND (IHSR BIT 0)
TLWM (IHSR BIT 2)
MASTER STATUS REGISTERHDLC STATUS REGISTER
EVENT LATCH CLEAR ON MSR READ
DS3160
Figure 4.3F. SR1 STATUS BIT FLOW
HARDWARE
SIGNAL
SR1
STATUS BIT
(MSR BIT 5)RECEIVE LOS
SIGNAL FROM
FRAMER
LOS
(SR1 BIT 0)
LOS (ISR1 BIT 0)RECEIVE LOFSIGNAL FROM
FRAMER
LOF
(SR1 BIT 1)
LOF (ISR1 BIT 1)RECEIVE AIS
SIGNAL FROMFRAMER
AIS
(SR1 BIT 3)AIS (ISR1 BIT 3)RECEIVE RAI
SIGNAL FROM
FRAMER
RAI
(SR1 BIT 4)
RAI (ISR1 BIT 4)
LATCH
RECEIVE START
OF FRAMESIGNAL FROM
FRAMER
RSOFRSOF (ISR1 BIT 5)
TRANSMIT
START OF
FRAME
SIGNAL
FROM
FRAMER
TSOF
TSOF (ISR1 BIT 6)LATCH
LATCHRECEIVE CRCERROR SIGNAL
FROM FRAMER
CRCER
CRCER (ISR1 BIT 2)
RECEIVE
CHANGE OF
FRAME
ALIGNMENT
RCOFA
RCOFA (ISR1 BIT 7)
LATCH
REMOTE
END ALARM
DETECTED
READ
READ (ISR1 BIT 8)
LATCH
FALSE
FRAME
ALIGNMENT
DETECTED
FFA
FFA (ISR1 BIT 9)
SR1 STATUS REGISTERMASTER STATUS REGISTER
EVENT LATCH CLEAR ON MSR READ
DS3160
Register Name:IMSR
Register Description:Interrupt Mask for Master Status Register
Register Address:08h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Bit 0/One-Second-Timer Boundary Occurrence (OST)
0 = interrupt masked
1 = interrupt unmasked
Bit 1/Counter Overflow Event (COVF)
0 = interrupt masked
1 = interrupt unmasked
Bit 2/Change in BERT Status (BERT)
0 = interrupt masked
1 = interrupt unmasked
Bit 3/Change in HDLC Status (RHDLC)
0 = interrupt masked
1 = interrupt unmasked
Bit 4/Change in Framer/Formatter Status (SR1)0 = interrupt masked
1 = interrupt unmasked
Bit 8/Loss-of-Transmit Clock (LOTC)
0 = interrupt masked
1 = interrupt unmasked
Bit 10/Analog Loss-of-Signal Detected (LIULOS)
0 = interrupt masked
1 = interrupt unmasked
Bit 11/Transmit Driver Monitor (TXDRVR)
0 = interrupt masked
1 = interrupt unmasked
DS3160
5. FRAMER
5.1 General Description
On the receive side, the framer locates the frame boundaries of the incoming data stream and monitors the
data stream for alarms and errors. Alarms are detected and reported in status register 1 (SR1) and the
information register (INFO), which are described in Section 5.3. Errors are accumulated in a set of error
counters (Section 5.4). The host can force the framer to resynchronize by the REFRM control bit in CR1
(Section 5.2). On the transmit side, the device formats the outgoing data stream with the proper framing
pattern and overhead and can generate alarms. It can also inject errors for diagnostic testing purposes (see
the EIC register). The transmit side of the framer is called the formatter.
Line Loopback
The line loopback loops the incoming data (i.e., RCLK, RPOS, and RNEG inputs) directly back to the
transmit side (i.e., TCLK, TPOS, and TNEG outputs; Figure 1B). When this loopback is enabled, the
incoming receive data continues to pass through the device, but the data output from the formatter is
replaced with the data being input to the device. (See the block diagrams in Section 1 for a visual
description of this loopback.)
Diagnostic Loopback
The diagnostic loopback loops the outgoing data from the formatter back to the receive side framer. When
this loopback is enabled, the incoming receive data at RCLK, RPOS, and RNEG is ignored. (See the
block diagrams in Section 1 for a visual description of this loopback.) Note that the device can still
generate AIS at the TCLK, TPOS, and TNEG outputs when this loopback is invoked. This is important to
keep the data that is being looped back from disturbing downstream equipment.
Payload Loopback
The payload loopback loops the framed data from the receive side framer back to the transmit side
formatter. When this loopback is enabled, the incoming receive data continues to pass through the device
but the data normally being input to the formatter is ignored. The overhead bits are regenerated by the
formatter and inserted into the transmit stream. During payload loopback, the DS3160 internally connects
FRCLK to FTCLK and FRSOF to FTSOF (FTSOF is set to the input mode). Clock and start-of-frame
configurations are returned to user values when the loopback is disabled. (See the block diagrams in
Section 1 for a visual description of this loopback.)
DS3160
5.2 Framer Control Register Description
Register Name:CR1
Register Description:Control Register 1
Register Address:0Ah
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Payload Loopback Enable (PLB). See Figures 1A and 1B for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 1/TS97 and TS98 Signaling Pass Through Enable (SIGPASS). Setting the SIGPASS bit allows the
signaling bits contained in timeslots 97 and 98 on the FTD stream to pass transparently through the
transmit formatter. When SIGPASS is a logic 0, timeslots 97 and 98 are sourced from the transmit TS97
and TS98 signaling insertion register (TXTS9798).
Bit 2/Transmit Pass Through Enable (TPT).
0 = enable the formatter to insert framing and overhead bits
1 = formatter does not insert any framing or overhead bits
Bits 3 and 4/Timeslot Select Bits 0 and 1 (TSLOT0 and TSLOT1). These bits are used to determine
what timeslots are considered active by the signals FRDEN and FTDEN.
DS3160
Figure 5.2A. FRDEN AND FTDEN 6Mbps TIMING
Figure 5.2B. FRDEN AND FTDEN 4.5Mbps TIMING
Figure 5.2C. FRDEN AND FTDEN 3Mbps TIMING
FRDEN/ FTDEN
FRDEN/
FTDEN
FRDEN/
FTDEN
DS3160
Figure 5.2D. FRDEN AND FTDEN 1.5Mbps TIMING
Bit 5/Transmit Remote Alarm Indication (TRAI). When this bit is set high, the RAI pattern is sent on
the M-bit.
0 = do not transmit RAI
1 = transmit RAI
Bit 6/Automatic Transmit Remote Alarm Indication on LOS (TRAILOS). When this bit is set high,
the RAI pattern is sent on the M-bit automatically when the framer declares a loss-of-signal (LOS)
occurrence. Transmission of RAI terminates when LOS is cleared.
0 = disable automatic RAI transmit
1 = enable automatic RAI transmit
Bit 7/Automatic Transmit Remote Alarm Indication on LOF (TRAILOF). When this bit is set high,
the RAI pattern is sent on the M-bit automatically when the framer declares a loss-of-frame (LOF)
occurrence. Transmission of RAI terminates when LOF is cleared.
0 = disable automatic RAI transmit
1 = enable automatic RAI transmit
Bits 8/Frame Error-Counting Control Bit (FECC). This bit is used to control what events are counted
by the frame error counter. When this bit is set low, the counter accumulates LOF occurrences. When this
bit is set high, the counter accumulates F-bit errors.
Bit 9/Error-Counting Control (ECC). This bit is used to control whether the device increments the
error counters during LOF conditions. It affects the frame error counter only when it is configured to
count frame errors, not LOF occurrences. When this bit is set low, the frame error counter and CRC error
counter are not allowed to increment during LOF conditions. When this bit is set high, both counters are
allowed to increment during LOF conditions.
0 = stop the FECR and CRCCR error counters from incrementing during LOF
1 = allow the FECR and CRCCR error counters to increment during LOF
FRDEN/
FTDEN
DS3160
Bit 10/CRC-5 Framing Mode (CRC5FM). When set, this bit enables an alternate framing algorithm that
uses the CRC-5 check bits to validate framing in addition to the FAS bits. This reduces the chances of
falsely framing to an emulator pattern in the frame. This algorithm declares frame synchronization after
two or more of the first four FAS valid frames have correct CRC-5 check bits. If these criteria are not
met, reframe is initiated at the FAS level. If CRC5FM is set to 0, the framing algorithm only searches for
three consecutive multiframes with correct FAS patterns to declare frame synchronization.
0 = disable CRC qualified framing
1 = enable CRC qualified framing
Bit 14/Reframe (REFRM). The reframe bit forces the DS3160’s receiver to begin searching for a new
frame alignment. If the new frame alignment matches the previous alignment, there is no disruption in
data or movement of the data-enable and start-of-frame signals. A 0-to-1 transition triggers the reframing.
Bit 15/Auto Reframe (AREFRM). Setting the auto-reframe bit to a 0 allows the DS3160 to begin
searching for new frame alignment when an LOF has been declared.
0 = enable automatic reframe
1 = disable automatic reframe
DS3160
Register Name:CR2
Register Description:Control Register 2
Register Address:0Ch
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Bipolar Violation Insert (BPVI). A 0-to-1 transition on this bit causes a single BPV to be inserted
into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive 1’s to insert the BPV. This bit must be cleared and set again for a
subsequent error to be inserted. In the manual-error-insert mode (MEIMS = 1), errors are inserted on each
toggle of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors are
inserted.
Bit 1/Excessive Zero Insert (EXZI). A 0-to-1 transition on this bit causes a single EXZ event to be
inserted into the transmit data stream. An EXZ event is defined as eight or more consecutive 0’s. Once
this bit has been toggled from a 0 to a 1, the device waits for the next possible B8ZS code word insertion
and it suppresses that code word from being inserted and, hence, this creates the EXZ event. This bit must
be cleared and set again for a subsequent error to be inserted. In the manual-error-insert mode
(MEIMS = 1), errors are inserted on each toggle of the FTMEI input signal as long as this bit is set high.
When this bit is set low, no errors are inserted.
Bit 2/Frame Bit-Error Insert (FBEI). A 0-to-1 transition on this bit causes the transmit formatter to
generate a framing bit error. Once this bit has been toggled from a 0 to a 1, the device waits for the next
possible framing bit to insert the error. This bit must be cleared and set again for a subsequent error to be
inserted. In the manual-error-insert mode (MEIMS = 1), errors are inserted on each toggle of the FTMEI
input signal as long as this bit is set high. When this bit is set low, no errors are inserted. Only FAS bits
are corrupted by this function.
Bit 3/Loss-of-Frame Error Insert (LOFI). A 0-to-1 transition on this bit causes the transmit formatter
to generate seven consecutive multiframes with errors in the FAS pattern. Once this bit has been toggled
from a 0 to a 1, the device waits for the next multiframe to begin error insertion. This bit must be cleared
and set again for a subsequent error to be inserted. In the manual-error-insert mode (MEIMS = 1), errors
are inserted on each toggle of the FTMEI input signal as long as this bit is set high. When this bit is set
low, no errors are inserted. Only FAS bits are corrupted by this function.
DS3160
Bit 4/CRC Error Insert (CRCI). A 0-to-1 transition on this bit causes the transmit formatter to generate
a CRC-5 error. Once this bit has been toggled from a 0 to a 1, the device waits for the next possible CRC-
5 word to insert the error. This bit must be cleared and set again for a subsequent error to be inserted. In
the manual-error-insert mode (MEIMS = 1), errors are inserted on each toggle of the FTMEI input signal
as long as this bit is set high. When this bit is set low, no errors are inserted. Only CRC-5 bits are
corrupted by this function.
Bit 5/Manual-Error-Insert Mode Select (MEIMS). When this bit is set low, the device inserts errors on
each 0-to-1 transition of the BPVI, EXZI, or FBEI control bits. When this bit is set high, the device inserts
errors on each 0-to-1 transition of the FTMEI input signal. The appropriate BPVI, EXZI, or FBEI control
bit must be set to 1 for this to occur. If all of the BPVI, EXZI, and FBEI control bits are set to 0, no errors
are inserted.
0 = use 0-to-1 transition on the BPVI, EXZI, or FBEI control bits to insert errors
1 = use a 0-to-1 transition on the FTMEI input signal to insert errors
Bit 6/Alternate AIS Enable (ALTAIS). When set low, the device determines AIS using the default
criteria. When set high, the device determines AIS using the alternate criteria. See Table 5.3A, Alarm
Criteria, for additional details.
Bit 8/Remote-End Alarm Bit (A). When set low, the device inserts a 0 in the A-bit position (bit 788 of
the third frame in the multiframe). When set high, the device inserts a 1 in the A-bit position.
0 = set the A-bit to 0
1 = set the A-bit to 1
Bits 9, 10, 11/Spare Bits (X1, X2, X3). These control register bits determine what values are loaded into
the spare bit locations (bits 785, 786, 787) of the third frame in the multiframe. X1 maps into bit 785; X2
maps into bit 786; X3 maps into bit 787. These bits should be set to a 1 if not used.
0 = set the X-bit to 0
1 = set the X-bit to 1
Bit 12/Remote-End Alarm-Detected Threshold (RALMTH). This bit selects the number of
consecutive A-bits required to set and clear the remote-end alarm-detected status bit found in SR1.
0 = alarm set when the A-bit has been a logic 1 for three consecutive frames and reset when the A-bit
has been a logic 0 for three consecutive frames
1 = alarm set when the A-bit has been a logic 1 for five consecutive frames and reset when the A-bit
has been a logic 0 for five consecutive frames
DS3160
Bits 13 and 14/Loss-of-Signal Threshold Select Bits 0 and 1 (LOSTHR0 and LOSTHR1). These bits
are used to determine how many consecutive 0’s must be received in order to declare a loss-of-signal
(LOS) condition. See Table 5.3A, Alarm Criteria, for additional details.
Bit 15/Idle Timeslot Fill Select (IDLEFILL). This bit determines whether 1’s or 0’s are inserted into the
unused timeslots in the transmit path when the DS3160 is operated at fractional line rates. When this bit is
set low, the unused channels are filled with 1’s. When this bit is set high, the unused channels are filled
with 0’s.
DS3160
Register Name:TXTS9798
Register Description:Transmit TS97 and TS98 Signaling Insertion
Register Address:0Eh
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/Transmit TS97 Signaling (TS97_1:TS97_8). These bits are used to set the contents of
timeslot 97 (TS97) in the transmit data path. TS97_1 is the first bit of TS97 transmitted.
Bits 8 to 15/Transmit TS98 Signaling (TS98_1:TS98_8). These bits are used to set the contents of
timeslot 98 (TS98) in the transmit data path. TS98_1 is the first bit of TS98 transmitted.
Note: No synchronization of the insertion of the TXTS9798 register contents with respect to the frame or
timeslot is provided.
DS3160
Register Name:RXTS9798
Register Description:Receive TS97 and TS98 Monitor
Register Address:10h
Bit #
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/Receive TS97 Signaling (TS97_1:TS97_8). These bits contain the contents of timeslot 97
(TS97) in the receive data path. TS97_1 is the first bit of TS97 received.
Bits 8 to 15/Receive TS98 Signaling (TS98_1:TS98_8). These bits contain the contents of timeslot 98
(TS98) in the receive data path. TS98_1 is the first bit of TS98 received.
Note: The RXTS9798 register contents are real-time and are not integrated. Register content updates are
not synchronized with byte, frame, or multiframe boundaries.
DS3160
5.3 Framer Status and Interrupt Register Descriptions
Note: See Figure 5.3A for details about the signal flow for the status bits in the SR register.
Register Name:SR1
Register Description:Status Register
Register Address:12h
Bit #76543210
Name
Default
Bit #15141312111098
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Loss-of-Signal Occurrence (LOS). This latched read-only alarm-status bit is set to a 1 when the
framer detects a loss of signal. The signal FRD is forced to all 1’s during an LOS condition. This bit is
cleared when read unless an LOS condition still exists. A change in state of the LOS can cause a hardware
interrupt to occur if the LOS bit in the interrupt mask for the SR1 (ISR1) register is set to a 1 and the SR1
bit in the interrupt mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when
this bit is read. The LOS alarm criteria is described in Table 5.3A.
Bit 1/Loss-of-Frame Occurrence (LOF). This latched read-only alarm-status bit is set to a 1 when the
framer detects a loss of frame. This bit is cleared when read unless an LOF condition still exists. A change
in state of the LOF can cause a hardware interrupt to occur if the LOF bit in the interrupt mask for the
SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for the MSR (IMSR) register is set
to a 1. The interrupt is allowed to clear when this bit is read. The LOF alarm criteria is described in Table
5.3A.
Bit 2/Receive CRC Error Detected (CRCER). This latched read-only event-status bit is set to a 1 as a
result of detecting a CRC error in a received multiframe. This bit is cleared when read. The setting of this
bit can cause a hardware interrupt to occur if the CRCER bit in the interrupt mask for the SR1 (ISR1)
register is set to a 1 and the SR1 bit in the interrupt mask for the MSR (IMSR) register is set to a 1.
Bit 3/Alarm Indication Signal Detected (AIS). This latched read-only alarm-status bit is set to a 1 when
the framer detects an incoming alarm indication signal. This bit is cleared when read unless an AIS signal
is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS
bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for
MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is read. The AIS alarm
detection criteria is described in Table 5.3A.
Bit 4/Remote Alarm Indication Detected (RAI). This latched read-only alarm-status bit is set to a 1
when the framer detects an incoming remote alarm indication (RAI) signal. This bit is cleared when read
DS3160
interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is
read. The RAI alarm detection criteria is described in Table 5.3A.
Bit 5/Transmit Start of Frame (TSOF). This latched read-only event-status bit is set to a 1 on each
transmit frame or multiframe boundary (see FTSOFM). This bit is a software version of the FTSOF
hardware signal and it is cleared when read. The setting of this bit can cause a hardware interrupt to occur
if the TSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for MSR (IMSR) register is set to a 1.
Bit 6/Receive Start of Frame (RSOF). This latched read-only event-status bit is set to a 1 on each
receive frame or multiframe boundary (see FRSOFM). This bit is a software version of the FRSOF
hardware signal and it is cleared when read. The setting of this bit can cause a hardware interrupt to occur
if the RSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for MSR (IMSR) register is set to a 1.
Bit 7/Receive Change-of-Frame Alignment (RCOFA). This latched read-only event-status bit is set to a
1 when the framer has experienced a change-of-frame alignment (COFA). A COFA occurs when the
device achieves synchronization in a different alignment than it had previously. If the device has never
acquired synchronization before, then this status bit is meaningless. This bit is cleared when read and is
not set again until the framer has lost synchronization and reacquired synchronization in a different
alignment. The setting of this bit can cause a hardware interrupt to occur if the RCOFA bit in the interrupt
mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for MSR (IMSR) register
is set to a 1.
Bit 8/Remote-End Alarm Detected (READ). This latched read-only alarm-status bit is set to a 1 when
the framer detects a remote-end alarm (A-bit set to 1). This bit is cleared when read unless the remote-end
alarm signal is present. A change in state of the remote-end alarm can cause a hardware interrupt to occur
if the READ bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is read. The
READ threshold can be set in CR2.
Bit 9/False-Frame Alignment (FFA). This latched read-only event-status bit is set to a 1 when 32
consecutive super frames have bad CRC. This feature can be used to assist in monitoring for false-frame
alignment as described in JT-G706. This bit is cleared when read. The setting of this bit can cause a
hardware interrupt to occur if the RSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and
the SR1 bit in the interrupt mask for the MSR (IMSR) register is set to a 1.

Partno	Mfg	Dc	Qty	Available	Descript
DS3160	DALLAS	N/a	898	avai	JT 6312kbps Secondary-Rate Line Interface Unit and Framer/Formatter