DS2760AE-025+ ,High-Precision Li+ Battery MonitorPIN DESCRIPTION Current accumulation CC - Charge control output - Internal sense resistor: 0.25m ..
DS2760BE , High-Precision Li Battery Monitor
DS2760BE+ ,High-Precision Li+ Battery MonitorFEATURES PIN ASSIGNMENT 1 2 3 4Li+ safety circuit - Overvoltage protection ..
DS2760BE+025 , High-Precision Li Battery Monitor
DS2761AE ,High-Precision Li+ Battery MonitorPIN DESCRIPTIONRangeCC - Charge Control Output Current Accumulation:DC - Discharge Control Output- ..
DS2761AE+025 ,High-Precision Li+ Battery Monitorfeatures a programmable I/O pin that allows the host system to sense and control other electronics ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS2760AE-025+-DS2760BE+
High-Precision Li+ Battery Monitor
FEATURES Li+ safety circuit
- Overvoltage protection Overcurrent/short circuit protection
- Undervoltage protection
Zero Volt Battery Recovery Charge
Available in two configurations:
- Internal 25m sense resistor
- External user-selectable sense resistor
Current measurement 12-bit bidirectional measurement Internal sense resistor configuration:
0.625mA LSB and ±1.9A dynamic range External sense resistor configuration:
15.625V LSB and ±64mV dynamic range
Current accumulation Internal sense resistor: 0.25mAhr LSB External sense resistor: 6.25Vhr LSB
Voltage measurement with 4.88mV resolution
Temperature measurement using integrated
sensor with 0.125C resolution
System power management and control feature
support
32 bytes of lockable EEPROM
16 bytes of general purpose SRAM
Dallas 1-Wire® interface with unique 64-bit
device address
Low power consumption: Active current: 90A max Sleep current: 2A max
PIN ASSIGNMENT
PIN DESCRIPTION - Charge control output - Discharge control output
DQ - Data input/output
PIO - Programmable I/O pin
PLS - Battery pack positive terminal input - Power switch sense input
VIN - Voltage sense input
VDD - Power supply input (2.5V to 5.5V)
VSS - Device ground
SNS - Sense resistor connection
IS1 - Current sense input
IS2 - Current sense input
SNS Probe - Do not connect
VSS Probe - Do not connect
DS2760
High-Precision Li+ Battery Monitor
VIN
VDD
PIO
VSS
VSS
VSS
PS
IS1
DS2760
16-Pin TSSOP Package
IS2
SNS
SNS3
SNS
PLS
DS2760
Flip-Chip Packaging
Top View
1-Wire is a registered trademark of Dallas Semiconductor.
PLS DC DQ
CC IS2
VIN IS1
VDD PIO PS
SNS
VSS
1 2 3 4
SNS
Probe
VSS
Probe
DS2760
ORDERING INFORMATION
Part Marking Description DS2760AE+ DS2760A TSSOP, External Sense Resistor, 4.275V Vov, Lead-Free
DS2760BE+ DS2760B TSSOP, External Sense Resistor, 4.35V Vov, Lead-Free
DS2760AE+T&R DS2760A DS2760AE+ on Tape & Reel, Lead-Free
DS2760 BE+T&R DS2760B DS2760BE+ on Tape & Reel, Lead-Free
DS2760AE+025 2760A25 TSSOP, 25m Sense Resistor, 4.275V Vov, Lead-Free
DS2760BE+025 2760B25 TSSOP, 25m Sense Resistor, 4.35V Vov, Lead-Free
DS2760AE+025/T&R 2760A25 DS2760AE+025 in Tape & Reel, Lead-Free
DS2760BE+025/T&R 2760B25 DS2760BE+025 in Tape & Reel, Lead-Free
DS2760AX DS2760A Flipchip, External Sense Resistor, Tape & Reel, 4.275V Vov
DS2760BX DS2760B Flipchip, External Sense Resistor, Tape & Reel, 4.35V Vov
DS2760AX-025 DS2760AR Flipchip, 25m Sense Resistor, Tape & Reel, 4.275V Vov
DS2760BX-025 DS2760BR Flipchip, 25m Sense Resistor, Tape & Reel, 4.35V Vov
DS2760AE DS2760A TSSOP, External Sense Resistor, 4.275V Vov
DS2760BE DS2760B TSSOP, External Sense Resistor, 4.35V Vov
DS2760AE/T&R DS2760A DS2760AE on Tape & Reel
DS2760 BE/T&R DS2760B DS2760BE on Tape & Reel
DS2760AE-025 2760A25 TSSOP, 25m Sense Resistor, 4.275V Vov
DS2760BE-025 2760B25 TSSOP, 25m Sense Resistor, 4.35V Vov
DS2760AE-025/T&R 2760A25 DS2760AE-025 in Tape & Reel
DS2760BE-025/T&R 2760B25 DS2760BE-025 in Tape & Reel
DESCRIPTION The DS2760 High-Precision Li+ Battery Monitor is a data acquisition, information storage, and safety
protection device tailored for cost-sensitive battery pack applications. This low-power device integrates
precise temperature, voltage, and current measurement, nonvolatile data storage, and Li+ protection into
the small footprint of either a TSSOP package or flip chip. The DS2760 is a key component in
applications including remaining capacity estimation, safety monitoring, and battery-specific data storage.
Via its 1-Wire interface, the DS2760 gives the host system read/write access to status and control
registers, instrumentation registers, and general purpose data storage. Each device has a unique factory-
programmed 64-bit net address which allows it to be individually addressed by the host system,
supporting multi-battery operation.
The DS2760 is capable of performing temperature, voltage and current measurement to a resolution
sufficient to support process monitoring applications such as battery charge control, remaining capacity
estimation, and safety monitoring. Temperature is measured using an on-chip sensor, eliminating the need
for a separate thermistor. Bidirectional current measurement and accumulation are accomplished using
either an internal 25m sense resistor or an external device. The DS2760 also features a programmable
I/O pin that allows the host system to sense and control other electronics in the pack, including switches,
vibration motors, speakers and LEDs.
Three types of memory are provided on the DS2760 for battery information storage: EEPROM, lockable
EEPROM and SRAM. EEPROM memory saves important battery data in true nonvolatile memory that
is unaffected by severe battery depletion, accidental shorts or ESD events. Lockable EEPROM becomes
DS2760
BLOCK DIAGRAM Figure 1 1-WIRE
INTERFACE
AND
ADDRESS
THERMAL
SENSE
MUX
VOLTAGE
REFERENCE
ADC
REGISTERS AND
USER MEMORY
25m
chip ground
LOCKABLE EEPROM
SRAM
TEMPERATURE
VOLTAGE
CURRENT
ACCUM. CURRENT
STATUS / CONTROL
LI+ PROTECTION
VIN
IS1
IS2
SNS
IS2IS1
VSS
PLS
PIO
TIMEBASE
internal sense resistor configuration only
DS2760
DETAILED PIN DESCRIPTION Table 1
SYMBOL TSSOP* FLIP
CHIP*
DESCRIPTION 1 C1
Charge Protection Control Output. Controls an external p-channel high-side charge protection FET.
DC 3 B2
Discharge Protection Control Output. Controls an external p-channel high-side discharge protection FET.
DQ 7 B4
Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the DATA terminal of the battery pack. Pin has an internal
1A pull-down for sensing disconnection.
PIO 14 E2
Programmable I/O Pin. Used to control and monitor user-defined
external circuitry. Open drain to VSS.
PLS 2 B1
Battery Pack Positive Terminal Input. The device monitors the state of the battery pack’s positive terminal through this pin in order to detect
events such as the attachment of a charger or the removal of a short
circuit. Additionally, a charge path to recover a deeply depleted cell is
provided from PLS to VDD. 10 E4
Power Switch Sense Input. The device wakes up from Sleep Mode when it senses the closure of a switch to VSS on this pin. Pin has an
internal 1A pull-up to VDD.
VIN 16 D1
Voltage Sense Input. The voltage of the Li+ cell is monitored via this input pin. This pin has a weak pullup to VDD.
VDD 15 E1
Power Supply Input. Connect to the positive terminal of the Li+ cell through a decoupling network.
VSS 11,12,13 F3
Device Ground. Connect directly to the negative terminal of the Li+ cell. For the external sense resistor configuration, connect the sense resistor
between VSS and SNS.
SNS 4,5,6 A3
Sense Resistor Connection. Connect to the negative terminal of the battery pack. In the internal sense resistor configuration, the sense resistor
is connected between VSS and SNS.
IS1 9 D4
Current Sense Input. This pin is internally connected to VSS through a 4.7k resistor. Connect a 0.1F capacitor between IS1 and IS2 to
complete a low-pass input filter.
IS2 8 C4
Current Sense Input. This pin is internally connected to SNS through a 4.7k resistor.
SNS
Probe
N/A C2
Do Not Connect. VSS
Probe
N/A D2
Do Not Connect. * Mechanical drawing for the 16-pin TSSOP and DS2760 flip-chip package can be found at:
DS2760
APPLICATION EXAMPLE Figure 2 1 – RSENS is present for external sense resistor configurations only
2 – RSENSINT is present for internal sense resistor configurations only
SNS
DS2760
VSS
IS2IS1
voltage sense
RSENSINT(2) RKSRKS
PACK+
PACK-
DATA
150
150 1k
150
1k 1k
DS2760
104
CC
PLS
DC
SNS
SNS
SNS
DQ
IS2
VIN
VDD
PIO
VSS
VSS
VSS
PS
IS1
102
BAT+
BAT-
RSENS(1)
4.7k
DS2760
POWER MODES The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually
measures current, voltage and temperature to provide data to the host system and to support current
accumulation and Li+ safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The
DS2760 enters Sleep Mode when any of the following conditions occurs:
the PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than
2 seconds (pack disconnection)
the voltage on VIN drops below undervoltage threshold VUV for tUVD (cell depletion)
the pack is disabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 returns to Active Mode when any of the following occurs:
the PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high
(pack connection)
the PS pin is pulled low (power switch)
the voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit
set to 0
the pack is enabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 defaults to Sleep Mode when power is first applied.
LI+ PROTECTION CIRCUITRY During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and
summarized in Table 2 and Figure 3.
LI+ PROTECTION CONDITIONS AND DS2760 RESPONSES Table 2
Activation Condition
Name Threshold Delay Response
Release
Threshold Overvoltage VIN > VOV tOVD CC high VIN < VCE
Undervoltage VIN < VUV tUVD CC, DC high,
Sleep Mode
VPLS > VDD(1)
(charger connected)
Overcurrent, Charge VIS > VOC(2) tOCD CC, DC high VPLS < VDD – VTP(3)
Overcurrent, Discharge VIS < -VOC(2) tOCD DC high VPLS > VDD – VTP(4)
Short Circuit VSNS > VSC tSCD DC high VPLS > VDD – VTP(4)
VIS = VIS1 – VIS2. Logic high = VPLS for CC and VDD for DC. All voltages are with respect to VSS. ISNS
references current delivered from pin SNS.
(1) If VDD <2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD
charges the battery and allows VDD to exceed 2.2V.
(2) for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of
current: ISNS > IOC for charge direction and ISNS < -IOC for discharge direction
(3) with test current ITST current flowing from PLS to VSS (pull-down on PLS)
(4) with test current ITST current flowing from VDD to PLS (pull-up on PLS)
Overvoltage. If the voltage of the cell exceeds overvoltage threshold VOV for a period longer than
DS2760
charge FET back on (unless another protection condition prevents it). Discharging remains enabled
during overvoltage.
Undervoltage. If the voltage of the cell drops below undervoltage threshold VUV for a period longer than undervoltage delay tUVD, the DS2760 shuts off the charge and discharge FETs, sets the UV flag in the
Protection Register, and enters Sleep Mode. The DS2760 provides a current-limited (IRC) recovery
charge path from PLS to VDD to gently charge severely depleted cells. The recovery path is enabled
when 0 VDD < 3V(typ). Once VDD reaches 3V(typ), the DS2760 will return to normal operation,
awaiting connection of a charger to turn on the charge FET and pull out of Sleep Mode.
Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (VIS = VIS1 – VIS2) is the filtered voltage drop across the current sense resistor. If VIS exceeds overcurrent threshold
VOC for a period longer than overcurrent delay tOCD, the DS2760 shuts off both external FETs and sets the
COC flag in the Protection Register. The charge current path is not re-established until the voltage on the
PLS pin drops below VDD – VTP. The DS2760 provides a test current of value ITST from PLS to VSS to
pull PLS down in order to detect the removal of the offending charge current source.
Overcurrent, Discharge Direction. If VIS is less than –VOC for a period longer than tOCD, the DS2760 shuts off the external discharge FET and sets the DOC flag in the Protection Register. The discharge
current path is not re-established until the voltage on PLS rises above VDD – VTP. The DS2760 provides a
test current of value ITST from VDD to PLS to pull PLS up in order to detect the removal of the offending
low-impedance load.
Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short circuit threshold VSC for a period longer than short circuit delay tSCD, the DS2760 shuts off the external discharge FET and sets the
DOC flag in the Protection Register. The discharge current path is not re-established until the voltage on
PLS rises above VDD – VTP. The DS2760 provides a test current of value ITST from VDD to PLS to pull
PLS up in order to detect the removal of the short circuit.
LITHIUM-ION PROTECTION CIRCUITRY EXAMPLE WAVEFORMS Figure 3 Sleep
Mode
VOV
VCE
VUV
VCELL
VIS
charge
discharge
-VSC
VOC
-VOC
0
tSCDtOCD
tOCD
tUVD
tOVDVPLS
VDD
active
VSS
VSS
inactive
tOVD
(1)
DS2760
Summary. All of the protection conditions described above are OR’ed together to affect the CC and DC
outputs. DC = (Undervoltage) or (Overcurrent, EITHER Direction) or (Short Circuit) or
(Protection Register bit DE = 0) or (Sleep Mode) = (Overvoltage) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register
bit CE = 0) or (Sleep Mode)
CURRENT MEASUREMENT In the Active Mode of operation, the DS2760 continually measures the current flow into and out of the
battery by measuring the voltage drop across a current sense resistor. The DS2760 is available in two
configurations: (1) internal 25m current sense resistor, and (2) external user-selectable sense resistor. In
either configuration, the DS2760 considers the voltage difference between pins IS1 and IS2 (VIS = VIS1 –
VIS2) to be the filtered voltage drop across the sense resistor. A positive VIS value indicates current is
flowing into the battery (charging), while a negative VIS value indicates current is flowing out of the
battery (discharging).
VIS is measured with a signed resolution of 12-bits. The current register is updated in two’s complement
format every 88ms (128/fsample) with an average of 128 readings. Currents outside the range of the
register are reported at the limit of the range. The format of the Current Register is shown in Figure 4.
For the internal sense resistor configuration, the DS2760 maintains the Current Register in units of Amps,
with a resolution of 0.625mA and full scale range of no less than 1.9A (see Note 7 on IFS spec for more
details). The DS2760 automatically compensates for internal sense resistor process variations and
temperature effects when reporting current.
For the external sense resistor configuration, the DS2760 writes the measured VIS voltage to the Current
Register, with a resolution of 15.625V and a full scale range of 64mV.
CURRENT REGISTER FORMAT Figure 4 MSB—Address 0E LSb—Address 0F
S 211 210 29 28 27 26 25 24 23 22 21 20 X X X
MSb LSb MSb LSb
Units: 0.625 mA for internal sense resistor
15.625 V for external sense resistor
CURRENT ACCUMULATOR The Current Accumulator facilitates remaining capacity estimation by tracking the net current flow into
and out of the battery. Current flow into the battery increments the Current Accumulator while current
flow out of the battery decrements it. Data is maintained in the Current Accumulator in two’s-
complement format. The format of the Current Accumulator is shown in Figure 5.
DS2760
resistor, the DS2760 maintains the Current Accumulator in units of Volt-hours, with a resolution of
6.25 Vhrs and a full scale range of 205 mVhrs.
The Current Accumulator is a read/write register that can be altered by the host system as needed.
CURRENT ACCUMULATOR FORMAT Figure 5 MSB—Address 10 LSb—Address 11
S 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
MSb LSb MSb LSb
Units: 0.25 mAhrs for internal sense resistor
6.25 Vhrs for external sense resistor
CURRENT OFFSET COMPENSATION Current measurement and the current accumulation are both internally compensated for offset on a
continual basis minimizing error resulting from variations in device temperature and voltage.
Additionally a constant bias may be utilized to alter any other sources of offset. This bias resides in
EEPROM address 33h in two’s-complement format and is subtracted from each current measurement.
The current offset bias is applied to both the internal and external sense resistor configurations. The
factory default for the current offset compensation is a value of 0.
CURRENT OFFSET BIAS Figure 6 Address 33
S 26 25 24 23 22 21 20
MSb LSb
Units: 0.625 mA for internal sense resistor
15.625 V for external sense resistor
VOLTAGE MEASUREMENT The DS2760 continually measures the voltage between pins VIN and VSS over a range of 0 to 4.75V.
The resulting data is placed in the Voltage Register in two’s-complement format with a resolution of
4.88mV. Voltages above the maximum register value are reported as the maximum value. The Voltage
Register format is shown in Figure 7.
VOLTAGE REGISTER FORMAT Figure 7 MSB—Address 0C LSb—Address 0D
S 29 28 27 26 25 24 23 22 21 20 X X X X X
MSb LSb MSb LSb
Units: 4.88 mV
DS2760
TEMPERATURE MEASUREMENT The DS2760 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the Temperature Register in two’s-complement format with a
resolution of 0.125°C over a range of 127°C. The Temperature Register format is shown in Figure 8.
TEMPERATURE REGISTER FORMAT Figure 8 MSB—Address 18 LSB—Address 19
S 29 28 27 26 25 24 23 22 21 20 X X X X X
MSb LSb MSb LSb
Units: 0.125C
PROGRAMMABLE I/O To use the PIO pin as an output, write the desired output value to the PIO bit in the Special Feature
Register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a
1 to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2760 turns off the PIO output driver and sets the
PIO high when it enters Sleep Mode or when DQ is low for more than 2 seconds, regardless of the state
of the PMOD bit.
POWER SWITCH INPUT The DS2760 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The PS pin, internally pulled to VDD through a 1A current source, is continuously
monitored for a low-impedance connection to VSS. If the DS2760 is in Sleep Mode, the detection of a
low on PS causes the device to transition into Active Mode, turning on the discharge FET. If the DS2760
is already in Active Mode, activity on PS has no effect other than the mirroring of its logic level in the bit in the Special Feature Register. The reading of a 0 in the PS bit should be immediately followed
by writing a 1 to the PS bit to ensure proper operation.
MEMORY The DS2760 has a 256-byte linear address space with registers for instrumentation, status and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general-purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the Protection Register, Status Register, and Current
Offset Register, respectively. When the MSB of any 2-byte register is read, both the MSB and LSB are
latched and held for the duration of the Read Data command to prevent updates during the read and
ensure synchronization between the two register bytes. For consistent results, always read the MSB and
the LSB of a two-byte register during the same Read Data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the Write Data
command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The
Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of
DS2760
MEMORY MAP Table 3
Address (Hex)
Description
Read/Write 00 Protection Register R/W
01 Status Register R
02-06 Reserved
07 EEPROM Register R/W
08 Special Feature Register R/W
09-0B Reserved
0C Voltage Register MSb R
0D Voltage Register LSb R
0E Current Register MSB R
0F Current Register LSb R
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSb R/W
12-17 Reserved
18 Temperature Register MSB R
19 Temperature Register LSb R
1A-1F Reserved
20-2F EEPROM, block 0 R/W*
30-3F EEPROM, block 1 R/W*
40-7F Reserved
80-8F SRAM R/W
90-FF Reserved
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER The Protection Register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, COC and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The default
values of the CE and DE bits of the Protection Register are stored in lockable EEPROM in the
corresponding bits in address 30h. A Recall Data command for EEPROM block 1 recalls the default
values of 1 into CE and DE. The format of the Protection Register is shown in Figure 9. The function of
each bit is described in detail in the following paragraphs.
PROTECTION REGISTER FORMAT Figure 9 Address 00
bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0
OV UV COC DOC CC DC CE DE
OV – Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition. This bit must be reset by the host system.
UV – Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
DS2760
COC – Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a charge-direction overcurrent condition. This bit must be reset by the host system.
DOC – Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a discharge-direction overcurrent condition. This bit must be reset by the host system.
– CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
– DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE – Charge Enable. Writing a 0 to this bit disables charging (CC output high, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2760 automatically sets this bit to 1 when it transitions
from Sleep Mode to Active Mode.
DE – Discharge Enable. Writing a 0 to this bit disables discharging (DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2760 automatically sets this bit to 1 when
it transitions from Sleep Mode to Active Mode.
STATUS REGISTER The default values for the Status Register bits are stored in lockable EEPROM in the corresponding bits
of address 31h. A Recall Data command for EEPROM block 1 recalls the default values into the Status
Register bits. The format of the Status Register is shown in Figure 10. The function of each bit is
described in detail in the following paragraphs.
STATUS REGISTER FORMAT Figure 10 Address 01
bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0
X X PMOD RNAOPSWEN X X X
PMOD – Sleep Mode Enable. A value of 1 in this bit enables the DS2760 to enter Sleep Mode when the DQ line goes low for greater than 2 seconds and leave Sleep Mode when the DQ line goes high. A value
of 0 disables DQ-related transitions into and out of Sleep Mode. This bit is read-only. The desired
default value should be set in bit 5 of address 31h. The factory default is 0.
RNAOP – Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h. The factory default is 0.
SWEN - SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP command. If set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of
address 31h. This bit is read-only. The factory default is 0.
DS2760
EEPROM REGISTER The format of the EEPROM Register is shown in Figure 11. The function of each bit is described in
detail in the following paragraphs.
EEPROM REGISTER FORMAT Figure 11 Address 07
bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0
EEC LOCK X X X X BL1 BL0
EEC – EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data command is in
progress. While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that
data may be written to unlocked EEPROM blocks.
LOCK – EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this bit enables the Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The
factory default is 0.
BL1 – EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 1
(addresses 30-3F) is locked (read-only) while a 0 indicates Block 1 is unlocked (read/write).
BL0 – EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 0
(addresses 20-2F) is locked (read-only) while a 0 indicates Block 0 is unlocked (read/write).
X – Reserved bits.
SPECIAL FEATURE REGISTER The format of the Special Feature Register is shown in Figure 12. The function of each bit is described in
detail in the following paragraphs.
SPECIAL FEATURE REGISTER FORMAT Figure 12 Address 08
bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0 PIO MSTR X X X X X
– PS Pin Mirror. This read-only bit mirrors the state of the PS pin. The reading of a 0 in this bit
should be immediately followed by writing a 1 to this location to insure proper operation.
PIO – PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.
MSTR - SWAP Master Status Bit. This bit indicates whether a device has been selected through the
SWAP command. Selection of this device through the SWAP command and the appropriate Net Address
will result in setting this bit, indicating that this device is the master. A 0 signifies that this device is not
the master.
