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DS26556-DS26556N
4-Port Cell/Packet Over T1/E1/J1 Transceiver
GENERAL DESCRIPTION The DS26556 is a quad, software-selectable T1,
E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters
+ LIUs, and a UTOPIA (cell), POS-PHY
(packet), and TDM backplane interface. Each framer has an HDLC controller that can be
mapped to any DS0 or FDL (T1)/Sa (E1) bit. The
DS26556 also includes full-featured BERT
devices per port, and an internal clock adapter useful for creating synchronous, high-frequency
backplane timing. The DS26556 is controlled
through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola
operation.
APPLICATIONS Routers IMA
Add-Drop Multiplexers ATM
DSLAMs WAN Interface
PBXs
Switches
Customer-Premise
Equipment
Central Office
Equipment
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
FEATURES Four Independent, Full-Featured T1/E1/J1 Transceivers UTOPIA 2 and 3 Cell Interface POS-PHY 2 and 3 Packet Interface TDM Backplane Supports TDM Bus Rates
from 1.544MHz to 16.384MHz Alarm Detection and Insertion Full-Featured BERT for Each Port AMI, B8ZS, HDB3, NRZ Line Coding Transmit Synchronizer BOC Message Controller (T1) One HDLC Controller per Framer Performance Monitor Counters RAI-CI and AIS-CI Support Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz JTAG Test Port Single 3.3V Supply with 5V Tolerant Inputs 17mm x 17mm, 256-Pin BGA (1.00mm
Pitch)
ORDERING INFORMATION
DS26556
4-Port Cell/Packet Over T1/E1/J1
Transceiver
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
TABLE OF CONTENTS BLOCK DIAGRAMS 9 FEATURES 10 2.1 FRAMER/LIU................................................................................................................................................10
2.1.1 Framer/Formatter................................................................................................................................................10 2.1.2 Line Interface (LIU).............................................................................................................................................10
2.1.3 Clock Synthesizer...............................................................................................................................................11 2.1.4 HDLC Controllers................................................................................................................................................11 2.1.5 Test and Diagnostics..........................................................................................................................................11 2.2 CELL/PACKET INTERFACE.............................................................................................................................11
2.2.1 General...............................................................................................................................................................11 2.2.2 ATM....................................................................................................................................................................12
2.2.3 HDLC..................................................................................................................................................................12 2.3 CONTROL PORT...........................................................................................................................................12
BACKPLANE CONFIGURATION SCENERIOS 14 ACRONYMS AND GLOSSARY 18 PIN DESCRIPTIONS 19 5.1 SHORT PIN LIST...........................................................................................................................................19
5.2 DETAILED PIN LIST.......................................................................................................................................22
DEVICE CONFIGURATION 30 FUNCTIONAL PIN TIMING 31 7.1 RECEIVER FUNCTIONAL TIMING DIAGRAMS....................................................................................................31 7.2 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS..............................................................................................32
7.3 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE FUNCTIONAL TIMING............................................................34 7.3.1 UTOPIA Level 2 Functional Timing.....................................................................................................................34 7.3.2 UTOPIA Level 3 Functional Timing.....................................................................................................................38
7.3.3 POS-PHY Level 2 Functional Timing..................................................................................................................41 7.3.4 POS-PHY Level 3 Functional Timing..................................................................................................................45
FUNCTIONAL DESCRIPTION 47 8.1 CELL / PACKET INTERFACE DESCRIPTION......................................................................................................47
8.1.1 Reset Descriptions..............................................................................................................................................47 8.1.2 BIT / BYTE Ordering...........................................................................................................................................47 8.2 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE............................................................................................47
8.2.1 General Description............................................................................................................................................47 8.2.2 Features..............................................................................................................................................................48 8.2.6 System Interface Bus Controller.........................................................................................................................48
8.3 ATM CELL / HDLC PACKET PROCESSING....................................................................................................52 8.3.1 General Description............................................................................................................................................52 8.3.2 Features..............................................................................................................................................................52
8.3.3 Transmit Cell/Packet Processor.........................................................................................................................53 8.3.4 Receive Cell/Packet Processor..........................................................................................................................53 8.3.5 Cell Processor....................................................................................................................................................54
8.3.6 Packet Processor................................................................................................................................................59 8.3.7 FIFO....................................................................................................................................................................61 8.3.8 System Loopback...............................................................................................................................................62
8.4 T1 RECEIVE FRAMER DESCRIPTION AND OPERATION....................................................................................63 8.4.1 T1 Loopbacks.....................................................................................................................................................63 8.4.2 H.100 (CT Bus) Compatibility.............................................................................................................................64
8.4.3 T1 Receive Status and Information....................................................................................................................65 8.4.4 Receive AIS-CI and RAI-CI Detection................................................................................................................67 8.4.5 T1 Receive-Side Digital Milliwatt Code Generation............................................................................................67
8.4.6 T1 Error Count Registers....................................................................................................................................67 8.4.7 T1 Receive Signaling Operation.........................................................................................................................68 8.4.8 Software Signaling..............................................................................................................................................68
8.4.9 Hardware Signaling............................................................................................................................................68 8.4.10 Signaling Re-insertion.........................................................................................................................................68
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.4.14 Receive SLC-96 Operation.................................................................................................................................69
8.4.15 Receive FDL.......................................................................................................................................................69 8.4.16 Programmable In-Band Loop-Code Detection....................................................................................................70 8.4.17 Receive HDLC Controller....................................................................................................................................70
8.4.18 Receive HDLC Controller Example.....................................................................................................................71 8.5 T1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION.............................................................................72 8.5.1 T1 Per-Channel Loopback..................................................................................................................................72
8.5.2 T1 Transmit DS0 Monitoring Function................................................................................................................72 8.5.3 T1 Transmit Signaling Operation........................................................................................................................72 8.5.4 T1 Transmit Per-Channel Idle Code Insertion....................................................................................................73
8.5.5 T1 Transmit Channel Mark Registers.................................................................................................................73 8.5.6 Fractional T1 Support (Gapped Clock Mode).....................................................................................................73 8.5.7 T1 Transmit Bit Oriented Code (BOC) Controller...............................................................................................73 8.5.8 T1 Transmit FDL.................................................................................................................................................73
8.5.9 Transmit SLC96 Operation...............................................................................................................................74 8.5.10 Transmit HDLC Controller...................................................................................................................................74 8.5.11 HDLC Transmit Example....................................................................................................................................74
8.5.12 Programmable In-Band Loop-Code Generator...................................................................................................75 8.5.13 Interfacing the T1 Tx Formatter to the BERT......................................................................................................76 8.5.14 T1 Transmit Synchronizer...................................................................................................................................76
8.6 E1 RECEIVE FRAMER DESCRIPTION AND OPERATION....................................................................................76 8.6.1 H.100 (CT Bus) Compatibility.............................................................................................................................76 8.6.2 E1 Error Count Registers....................................................................................................................................77
8.6.3 DS0 Monitoring Function....................................................................................................................................78 8.6.4 E1 Receive Signaling Operation.........................................................................................................................78 8.6.5 Fractional E1 Support (Gapped Clock Mode).....................................................................................................79
8.6.6 Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode)................................................................................79 8.6.7 HDLC Overhead Control Receive Example........................................................................................................79 8.6.8 Interfacing the E1 Rx Framer to the BERT.........................................................................................................80
8.6.9 E1 Transmit Formatter Description and Operation.............................................................................................81 8.6.10 Automatic Alarm Generation...............................................................................................................................81 8.6.11 G.706 Intermediate CRC-4 Updating (E1 Mode Only)........................................................................................81
8.6.12 E1 Transmit DS0 Monitoring Function................................................................................................................82 8.6.13 E1 Transmit Signaling Operation........................................................................................................................82 8.6.14 Fractional E1 Support (Gapped Clock Mode).....................................................................................................83
8.6.15 Additional (Sa) and International (Si) Bit Operation (E1 Mode)..........................................................................83 8.6.16 E1 Transmit HDLC Controller.............................................................................................................................83 8.6.17 E1 HDLC Transmit Example...............................................................................................................................84
8.6.18 Interfacing the E1 Transmitter to the BERT........................................................................................................85 8.6.19 E1 Transmit Synchronizer...................................................................................................................................85
LINE INTERFACE UNIT (LIU) 86 9.1 LIU TRANSMITTER........................................................................................................................................86
9.1.1 Pulse Shapes...................................................................................................................................................86 9.1.2 Transmit Termination.......................................................................................................................................86
9.1.3 Power-Down and High-Z.................................................................................................................................86 9.1.4 Transmit All Ones............................................................................................................................................86
9.1.5 Driver Fail Monitor............................................................................................................................................86 9.2 RECEIVER....................................................................................................................................................89
9.2.1 Receiver Monitor Mode...................................................................................................................................89 9.2.2 Peak Detector and Slicer................................................................................................................................90
9.2.3 Clock and Data Recovery...............................................................................................................................90 9.2.4 Receive Level Indicator...................................................................................................................................90
9.2.5 Loss of Signal...................................................................................................................................................90 9.3 JITTER ATTENUATOR....................................................................................................................................93
9.4 LIU LOOPBACKS..........................................................................................................................................93 9.4.1 Analog Loopback................................................................................................................................................93 9.4.2 Local Loopback...................................................................................................................................................94
9.4.3 Remote Loopback...............................................................................................................................................94
10 OVERALL REGISTER MAP 95
11 REGISTER MAPS AND DESCRIPTIONS 97
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.1.2 Global Status Registers....................................................................................................................................104
11.2 CELL / PACKET REGISTER DESCRIPTIONS...................................................................................................110 11.2.1 General Cell / Packet Registers........................................................................................................................111 11.2.2 Cell/Packet Status Registers............................................................................................................................113
11.2.3 Transmit FIFO Registers...................................................................................................................................115 11.2.4 Transmit Cell Processor Registers...................................................................................................................120 11.2.5 Transmit Packet Processor Registers..............................................................................................................127
11.2.6 Receive Cell Processor Registers....................................................................................................................133 11.2.7 Receive Packet Processor Registers...............................................................................................................148 11.2.8 Receive FIFO Registers...................................................................................................................................160 11.3 SYSTEM INTERFACE REGISTERS.................................................................................................................163
11.3.1 Transmit System Interface Registers................................................................................................................163 11.3.2 Receive System Interface Registers.................................................................................................................165
11.4 RECEIVE T1 FRAMER REGISTERS...............................................................................................................168 11.4.1 Receive Master-Mode Register........................................................................................................................171 11.4.2 Interrupt Information Register...........................................................................................................................172
11.4.3 T1 Receive Control Registers...........................................................................................................................173 11.4.4 T1 Line-Code Violation Count Register (LCVCR).............................................................................................189 11.4.5 T1 Path-Code Violation Count Register (PCVCR)............................................................................................190
11.4.6 T1 Frames Out-of-Sync Count Register (FOSCR)............................................................................................191 11.4.7 DS0 Monitoring Function..................................................................................................................................192 11.4.8 Receive Signaling Registers.............................................................................................................................193
11.4.9 T1 Receive Per-Channel Idle Code Insertion...................................................................................................196 11.4.10 T1 Receive Channel Mark Registers................................................................................................................197 11.4.11 Receive Fractional T1 Support (Gapped-Clock Mode).....................................................................................198 11.4.12 Receive T1 Bit-Oriented Code (BOC) Controller..............................................................................................199
11.4.13 Receive SLC-96 Operation...............................................................................................................................200 11.4.14 Receive FDL.....................................................................................................................................................201 11.4.15 Programmable In-Band Loop-Code Detection..................................................................................................202
11.4.16 Receive HDLC Controller..................................................................................................................................208 11.4.17 Receive BERT..................................................................................................................................................214 11.5 T1 TRANSMIT FRAMER................................................................................................................................216
11.5.1 Transmit-Master Mode Register.......................................................................................................................219 11.5.2 Interrupt Information Registers.........................................................................................................................219 11.5.3 T1 Transmit Control Registers..........................................................................................................................220
11.5.4 T1 Transmit Status and Information..................................................................................................................225 11.5.5 T1 Per-Channel Loopback................................................................................................................................228 11.5.6 T1 Transmit DS0 Monitoring Function..............................................................................................................229
11.5.7 T1 Transmit Signaling Operation......................................................................................................................229 11.5.8 T1 Transmit Per-Channel Idle Code Insertion..................................................................................................233 11.5.9 T1 Transmit Channel Mark Registers...............................................................................................................234
11.5.10 Fractional T1 Support (Gapped Clock Mode)...................................................................................................235 11.5.11 T1 Transmit Bit Oriented Code (BOC) Controller.............................................................................................236 11.5.12 T1 Transmit FDL...............................................................................................................................................237
11.5.13 Transmit SLC96 Operation.............................................................................................................................237 11.5.14 Transmit HDLC Controller.................................................................................................................................238 Transmit Interrupt Mask Register 2.................................................................................................................................243
11.5.15 Programmable In-Band Loop-Code Generator.................................................................................................244 11.5.16 Interfacing the T1 Tx Formatter to the BERT....................................................................................................246 11.5.17 T1 Transmit Synchronizer.................................................................................................................................248
11.6 E1 RECEIVE FRAMER.................................................................................................................................250 11.6.1 E1 Receive Framer Description and Operation................................................................................................253 11.6.2 Receive Master Mode Register.........................................................................................................................253
11.6.3 Interrupt Information Registers.........................................................................................................................254 11.6.4 E1 Receive Control Registers...........................................................................................................................254 11.6.5 E1 Receive Status and Information..................................................................................................................257
11.6.6 E1 Error Count Registers..................................................................................................................................269 11.6.7 DS0 Monitoring Function..................................................................................................................................272 11.6.8 E1 Receive Signaling Operation.......................................................................................................................273
11.6.9 E1 Receive Per-Channel Idle Code Insertion...................................................................................................275 11.6.10 E1 Receive Channel Mark Registers................................................................................................................276 11.6.11 Fractional E1 Support (Gapped Clock Mode)...................................................................................................276
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7 E1 TRANSMIT FRAMER................................................................................................................................293
11.7.1 Transmit Master Mode Register........................................................................................................................296 11.7.2 Interrupt Information Registers.........................................................................................................................297 11.7.3 E1 Transmit Control Registers..........................................................................................................................297
11.7.4 E1 Transmit Status and Information.................................................................................................................300 11.7.5 Per-Channel Loopback.....................................................................................................................................302 11.7.6 E1 Transmit DS0 Monitoring Function..............................................................................................................303
11.7.7 E1 Transmit Signaling Operation......................................................................................................................304 11.7.8 E1 Transmit Per-Channel Idle Code Insertion..................................................................................................308 11.7.9 E1 Transmit Channel Mark Registers...............................................................................................................309
11.7.10 Fractional E1 Support (Gapped Clock Mode)...................................................................................................309 11.7.11 Additional (Sa) and International (Si) Bit Operation (E1 Mode)........................................................................310 11.7.12 E1 Transmit HDLC Controller...........................................................................................................................317 11.7.13 Interfacing the E1 Transmitter to the BERT......................................................................................................323
11.7.14 E1 Transmit Synchronizer.................................................................................................................................325
12 LINE INTERFACE UNIT (LIU) 327 12.1 LIU REGISTERS.........................................................................................................................................328
13 BIT ERROR RATE TESTER (BERT) 335 13.1 BERT REGISTER BIT DESCRIPTIONS..........................................................................................................336
14 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 342 14.1 TAP CONTROLLER STATE MACHINE...........................................................................................................343 14.2 INSTRUCTION REGISTER.............................................................................................................................345
14.3 TEST REGISTERS.......................................................................................................................................346
15 PIN ASSIGNMENT 347
16 PACKAGE MECHANICAL INFORMATION 348
17 PACKAGE THERMAL INFORMATION 349
18 ABSOLUTE MAXIMUM RATINGS 350
19 AC TIMING 351 19.1 TRANSMIT TDM PORT AC CHARACTERISTICS.............................................................................................353 19.2 RECEIVE TDM PORT AC CHARACTERISTICS...............................................................................................354
19.3 HIGH SPEED PORT AC CHARACTERISTICS..................................................................................................355 19.4 SYSTEM INTERFACE AC CHARACTERISTICS.................................................................................................356 19.5 MICROPROCESSOR BUS AC CHARACTERISTICS..........................................................................................358
19.6 JTAG INTERFACE TIMING...........................................................................................................................361
20 REVISION CHANGE HISTORY 362
