DS26518G+ ,8-Port T1/E1/J1 TransceiverFeatures continued in Section 2. Maxim Integrated Products 1 Some revisions of this device may in ..
DS26518GN ,8-Port T1/E1/J1 Transceiverapplications. Each port is independently configurable, supporting Independent T1, E1, or J1 Selec ..
DS26518GNB1 ,8-Port T1/E1/J1 TransceiverApplications Channel Service Units (CSUs) Hitless Protection Switching Data Service Units (DSUs) ..
DS26519 ,16-Port T1/E1/J1 TransceiverApplications Routers Channel Service Units (CSUs) Hitless Protection Switching Data Service Unit ..
DS26521 ,Single T1/E1/J1 TransceiverFeatures Continued in Section 2. DS26521LN+ -40°C to +85°C 64 LQFP + Denotes lead-free/RoHS compli ..
DS26521DK ,Single T1/E1/J1 Transceiver Design Kit DS26521DK Single T1/E1/J1 Transceiver Design Kit
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26518G+-DS26518GN-DS26518GNB1
8-Port T1/E1/J1 Transceiver
Maxim Integrated Products 1 DS26518 -Port T1/E1/J1 Transceiver
______________General Description The DS26518 is an 8-port framer and line interface
unit (LIU) combination for T1, E1, J1 applications.
Each port is independently configurable, supporting
both long-haul and short-haul lines. The DS26518
Single-Chip Transceiver (SCT) is software and pinout
compatible with the 4-port DS26514. It is nearly
software compatible with the DS26528 and its
derivatives.
___________________Applications Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
______________Functional Diagram
DS26518
T1/J1/E1
TransceiverT1/E1/J1
NETWORK
BACKPLANE
TDM
_____________Ordering Information
PART TEMP RANGE PIN-PACKAGE DS26518GN -40°C to +85°C 256 TE-CSBGA
DS26518GN+ -40°C to +85°C 256 TE-CSBGA
+ Denotes a lead-free/RoHS compliant device.
________________________Features � Eight Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer) � Independent T1, E1, or J1 Selections for Each
Transceiver � Fully Internal Impedance Match, No External
Resistor � Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75Ω E1 Coaxial Applications � Hitless Protection Switching � Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411 � External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode � Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments � Transmit Open- and Short-Circuit Detection � LIU LOS in Accordance with G.775, ETS 300
233, and T1.231 � Transmit Synchronizer � Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port � Alarm Detection and Insertion � T1 Framing Formats of D4, SLC-96, and ESF � J1 Support � E1 G.704 and CRC-4 Multiframe �
T1-to-E1 Conversion
Features continued in Section 2.Rev: 103008
DS26518 8-Port T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9
2. FEATURE HIGHLIGHTS..................................................................................................10 2.1 GENERAL......................................................................................................................................10
2.2 LINE INTERFACE............................................................................................................................10
2.3 CLOCK SYNTHESIZERS..................................................................................................................10
2.4 JITTER ATTENUATOR.....................................................................................................................10
2.5 FRAMER/FORMATTER....................................................................................................................11
2.6 SYSTEM INTERFACE......................................................................................................................11
2.7 HDLC CONTROLLERS...................................................................................................................12
2.8 TEST AND DIAGNOSTICS................................................................................................................12
2.9 MICROCONTROLLER PARALLEL PORT.............................................................................................12
2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES............................................................12
3. APPLICATIONS...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE...................................................................................14
5. ACRONYMS AND GLOSSARY.......................................................................................16
6. MAJOR OPERATING MODES.........................................................................................17
7. BLOCK DIAGRAMS.........................................................................................................18
8. PIN DESCRIPTIONS........................................................................................................20 8.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................20
9. FUNCTIONAL DESCRIPTION.........................................................................................28 9.1 PROCESSOR INTERFACE................................................................................................................28
9.1.1 SPI Serial Port Mode............................................................................................................................28
9.1.2 SPI Functional Timing Diagrams.........................................................................................................28
9.2 CLOCK STRUCTURE.......................................................................................................................31
9.2.1 Backplane Clock Generation...............................................................................................................31
9.2.2 CLKO Output Clock Generation...........................................................................................................32
9.3 RESETS AND POWER-DOWN MODES..............................................................................................33
9.4 INITIALIZATION AND CONFIGURATION..............................................................................................34
9.4.1 Example Device Initialization and Sequence.......................................................................................34
9.5 GLOBAL RESOURCES....................................................................................................................34
9.6 PER-PORT RESOURCES................................................................................................................34
9.7 DEVICE INTERRUPTS.....................................................................................................................34
9.8 SYSTEM BACKPLANE INTERFACE...................................................................................................36
9.8.1 Elastic Stores.......................................................................................................................................36
9.8.2 IBO Multiplexing...................................................................................................................................39
9.8.3 H.100 (CT Bus) Compatibility..............................................................................................................45
9.8.4 Transmit and Receive Channel Blocking Registers.............................................................................47
9.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................47
9.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................47
9.9 FRAMERS......................................................................................................................................48
9.9.1 T1 Framing...........................................................................................................................................48
9.9.2 E1 Framing...........................................................................................................................................51
9.9.3 T1 Transmit Synchronizer....................................................................................................................53
9.9.4 Signaling..............................................................................................................................................54
DS26518 8-Port T1/E1/J1 Transceiver
9.9.8 Alarms..................................................................................................................................................65
9.9.9 Error Count Registers..........................................................................................................................67
9.9.10 DS0 Monitoring Function......................................................................................................................69
9.9.11 Transmit Per-Channel Idle Code Generation......................................................................................70
9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................70
9.9.13 Per-Channel Loopback........................................................................................................................70
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)...................................................................70
9.9.15 T1 Programmable In-Band Loop Code Generator...............................................................................71
9.9.16 T1 Programmable In-Band Loop Code Detection................................................................................72
9.9.17 Framer Payload Loopbacks.................................................................................................................73
9.10 HDLC CONTROLLERS................................................................................................................74
9.10.1 HDLC-64 Controller..............................................................................................................................74
9.10.2 Transmit HDLC-64 Controller..............................................................................................................78
9.10.3 HDLC-256 Controller............................................................................................................................80
9.11 POWER-SUPPLY DECOUPLING....................................................................................................84
9.12 LINE INTERFACE UNITS (LIUS)....................................................................................................85
9.12.1 LIU Operation.......................................................................................................................................87
9.12.2 Transmitter...........................................................................................................................................88
9.12.3 Receiver...............................................................................................................................................91
9.12.4 Hitless Protection Switching (HPS)......................................................................................................95
9.12.5 Jitter Attenuator....................................................................................................................................96
9.12.6 LIU Loopbacks.....................................................................................................................................97
9.13 BIT ERROR-RATE TEST FUNCTION (BERT)...............................................................................100
9.13.1 BERT Repetitive Pattern Set.............................................................................................................101
9.13.2 BERT Error Counter...........................................................................................................................101
10. DEVICE REGISTERS.....................................................................................................102 10.1 REGISTER LISTINGS.................................................................................................................102
10.1.1 Global Register List............................................................................................................................103
10.1.2 Framer Register List...........................................................................................................................104
10.1.3 LIU Register List.................................................................................................................................111
10.1.4 BERT Register List.............................................................................................................................112
10.1.5 HDLC-256 Register List.....................................................................................................................113
10.2 REGISTER BIT MAPS................................................................................................................114
10.2.1 Global Register Bit Map.....................................................................................................................114
10.2.2 Framer Register Bit Map....................................................................................................................115
10.2.3 LIU Register Bit Map..........................................................................................................................125
10.2.4 BERT Register Bit Map......................................................................................................................126
10.2.5 HDLC-256 Register Bit Map..............................................................................................................127
10.3 GLOBAL REGISTER DEFINITIONS...............................................................................................128
10.4 FRAMER REGISTER DESCRIPTIONS...........................................................................................145
10.4.1 Receive Register Descriptions...........................................................................................................145
10.4.2 Transmit Register Descriptions..........................................................................................................204
10.5 LIU REGISTER DEFINITIONS.....................................................................................................240
10.6 BERT REGISTER DEFINITIONS.................................................................................................250
10.6.1 Extended BERT Register Definitions.................................................................................................258
10.7 HDLC-256 REGISTER DEFINITIONS..........................................................................................262
10.7.1 Transmit HDLC-256 Register Definitions...........................................................................................262
10.7.2 Receive HDLC-256 Register Definitions............................................................................................267
11. FUNCTIONAL TIMING...................................................................................................272 11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................272
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................277
11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................282
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................286
DS26518 8-Port T1/E1/J1 Transceiver
12.1 THERMAL CHARACTERISTICS....................................................................................................292
12.2 LINE INTERFACE CHARACTERISTICS..........................................................................................292
13. AC TIMING CHARACTERISTICS..................................................................................293 13.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................293
13.1.1 SPI Bus Mode....................................................................................................................................293
13.2 JTAG INTERFACE TIMING.........................................................................................................303
14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT................................................304 14.1 TAP CONTROLLER STATE MACHINE.........................................................................................305
14.1.1 Test-Logic-Reset................................................................................................................................305
14.1.2 Run-Test-Idle.....................................................................................................................................305
14.1.3 Select-DR-Scan.................................................................................................................................305
14.1.4 Capture-DR........................................................................................................................................305
14.1.5 Shift-DR..............................................................................................................................................305
14.1.6 Exit1-DR.............................................................................................................................................305
14.1.7 Pause-DR...........................................................................................................................................305
14.1.8 Exit2-DR.............................................................................................................................................305
14.1.9 Update-DR.........................................................................................................................................305
14.1.10 Select-IR-Scan...............................................................................................................................305
14.1.11 Capture-IR......................................................................................................................................306
14.1.12 Shift-IR............................................................................................................................................306
14.1.13 Exit1-IR...........................................................................................................................................306
14.1.14 Pause-IR.........................................................................................................................................306
14.1.15 Exit2-IR...........................................................................................................................................306
14.1.16 Update-IR.......................................................................................................................................306
14.2 INSTRUCTION REGISTER...........................................................................................................308
14.2.1 SAMPLE:PRELOAD..........................................................................................................................308
14.2.2 BYPASS.............................................................................................................................................308
14.2.3 EXTEST.............................................................................................................................................308
14.2.4 CLAMP...............................................................................................................................................308
14.2.5 HIGHZ................................................................................................................................................308
14.2.6 IDCODE.............................................................................................................................................308
14.3 JTAG ID CODES......................................................................................................................309
14.4 TEST REGISTERS.....................................................................................................................309
14.4.1 Boundary Scan Register....................................................................................................................309
14.4.2 Bypass Register.................................................................................................................................309
14.4.3 Identification Register.........................................................................................................................309
15. PIN CONFIGURATION...................................................................................................310 15.1 PIN CONFIGURATION—256-BALL TE-CSBGA..........................................................................310
16. PACKAGE INFORMATION............................................................................................311
17. DOCUMENT REVISION HISTORY................................................................................312 DS26518 8-Port T1/E1/J1 Transceiver
LIST OF FIGURES Figure 7-1. Block Diagram.........................................................................................................................................18
Figure 7-2. Detailed Block Diagram...........................................................................................................................19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0...............................................29
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0...............................................29
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1...............................................29
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1...............................................29
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0...............................................30
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0...............................................30
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1...............................................30
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1...............................................30
Figure 9-9. Backplane Clock Generation...................................................................................................................31
Figure 9-10. Device Interrupt Information Flow Diagram...........................................................................................35
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz....................................................................................40
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz....................................................................................41
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz..................................................................................42
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode...............................................................................................46
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode...................................................................46
Figure 9-16. CRC-4 Recalculate Method..................................................................................................................70
Figure 9-17. Receive HDLC-64 Message Example...................................................................................................77
Figure 9-18. Transmit HDLC-64 Message Example..................................................................................................79
Figure 9-19. Receive HDLC-256 Message Example.................................................................................................82
Figure 9-20. Transmit HDLC-256 Message Example................................................................................................83
Figure 9-21. Network Connection—Longitudinal Protection.....................................................................................86
Figure 9-22. T1/J1 Transmit Pulse Templates..........................................................................................................89
Figure 9-23. E1 Transmit Pulse Templates...............................................................................................................90
Figure 9-24. Receive LIU Termination Options.........................................................................................................92
Figure 9-25. Typical Monitor Application...................................................................................................................93
Figure 9-26. HPS Block Diagram...............................................................................................................................95
Figure 9-27. Jitter Attenuation...................................................................................................................................96
Figure 9-28. Loopback Diagram................................................................................................................................97
Figure 9-29. Analog Loopback...................................................................................................................................97
Figure 9-30. Local Loopback.....................................................................................................................................98
Figure 9-31. Remote Loopback 2..............................................................................................................................98
Figure 9-32. Dual Loopback......................................................................................................................................99
Figure 11-1. T1 Receive-Side D4 Timing................................................................................................................272
Figure 11-2. T1 Receive-Side ESF Timing..............................................................................................................272
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)...............................................................273
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................273
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................274
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode..................................................................275
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode..............................................................276
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit....................................................................276
Figure 11-9. T1 Transmit-Side D4 Timing...............................................................................................................277
Figure 11-10. T1 Transmit-Side ESF Timing...........................................................................................................277
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................278
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................278
