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DS2460-DS2460S+
SHA-1 Coprocessor with EEPROM
3/10
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
GENERAL DESCRIPTION The DS2460 SHA-1 Coprocessor with EEPROM is a
hardware implementation of the ISO/IEC 10118-3
Secure Hash Algorithm (SHA-1), eliminating the need
to develop software to perform the complex SHA
computation required for authenticating SHA devices
and for performing the validation of digitally signed
service data. The DS2460 communicates with a
microcontroller through the popular I²C interface.
Applications include hosts of access control and
electronic payment systems for token authentication
and service data validation as well as generation of
one-time-use encryption keys for short message
encryption and decryption for messages not exceed-
ing the length of a SHA-1 result, which is 20 bytes.
APPLICATIONS License Management
Secure Feature Control
System Authentication
Clone Prevention
Door Locks
Utility Meters
TYPICAL OPERATING CIRCUIT VCC
SDA
SCL
GND
VCC
SDAAD0
SCL
AD1
AD2
GNDRP
VCC
FEATURES Dedicated Hardware-Accelerated SHA Engine
for Generating SHA-1 MACs 112 Bytes User EEPROM for Storing End
Equipment Property Data I²C Host Interface, Supports 100kHz and 400kHz
Communication Speeds Three Address Inputs for I²C Address
Assignment Single-Byte to 8-Byte EEPROM Write
Sequences 64-Bit Unique Registration Number EEPROM Endurance: 200k Cycles per 8-Byte
Block at 25°C 10ms max EEPROM Write Cycle Wide Operating Range: 2.7V to 5.5V,
-40°C to +85°C ±4kV IEC 1000-4-2 ESD Protection Level on All
Pins 8-Pin SO (150 mils) Package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2460S -40°C to +85°C 8 SO (150 mils)
DS2460S/T&R -40°C to +85°C 8 SO (150 mils)
DS2460S+ -40°C to +85°C 8 SO (150 mils)
DS2460S+T&R -40°C to +85°C 8 SO (150 mils)
+Denotes a lead(Pb)-free/RoHS-compliant package.
Request full data sheet at:
/fullds/DS2460
PIN CONFIGURATION VCC
SCL
SDA
N.C.
AD0
AD1
AD2
GND
DS2460
SHA-1 Coprocessor with EEPROM
Abridged Data Sheet
Abridged Data Sheet DS2460
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current Into Any Pin ±20mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Lead Temperature (soldering 10s) +300°C
Soldering Temperature (reflow) +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (-40°C to +85°C, see Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC 2.7 5.5 V
Bus idle 3 Standby Current ICCS Bus idle, +25°C 1 µA
Operating Current ICCA Bus active at 400kHz 250 500 µA
Programming Current IPROG (Note 9) 500 1000 µA
SHA-1 Computation Current ISHA See full version of data sheet mA
SHA-1 Engine SHA-1 Computation Time tSHA See full version of data sheet ms
EEPROM Programming Time tPROG 10 ms
Endurance NCYCLE At +25°C (Notes 2, 3) 200k
Data Retention tRET At +85°C (Notes 4, 5, 6) 40 years
I²C-Pins (Note 7) See Figure 6 LOW Level Input Voltage VIL (Note 8) -0.5 0.3 ×
VCC V
HIGH Level Input Voltage VIH (Notes 8, 9) 0.7 ×
VCC VCC +
0.5V V
Hysteresis of Schmitt Trigger
Inputs Vhys (Note 9) 0.05 ×
VCC V
LOW Level Output Voltage at
4mA Sink Current VOL 0.4 V
Output Fall Time from VIhmin to
VILmax with a Bus Capacitance
from 10pF to 400pF
tof (Note 9) 20 +
0.1Cb 250 ns
Pulse Width of Spikes that are
Suppressed by the Input Filter tSP SDA and SCL pins only
(Note 9) 50 ns
Input Current Each I/O Pin with
an Input Voltage Between
0.1VCCmax and 0.9VCCmax
Ii (Notes 8, 10) -10 10 µA
Input Capacitance Ci (Notes 8, 9) 10 pF
SCL Clock Frequency fSCL 0 400 kHz
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
tHD:STA 0.6 µs
LOW Period of the SCL Clock tLOW 1.3 µs
Abridged Data Sheet DS2460
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time for a Repeated
START Condition tSU:STA 0.6 µs
Data Hold Time tHD:DAT (Notes 11, 12) 0.9 µs
Data Setup Time tSU:DAT (Note 13) 100 ns
Setup Time for STOP ConditiontSU:STO 0.6 µs
Bus Free Time Between a
STOP and START Condition tBUF 1.3 µs
Capacitive Load for Each Bus
Line CB (Note 14) 400 pF
Note 1: Specification at -40°C is guaranteed by design and characterization only and not production tested.
Note 2: Write-cycle endurance is degraded as TA increases.
Note 3: Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 4: Data retention is degraded as TA increases.
Note 5: Guaranteed by 100% production test at elevated temperature for a shorter amount of time;
equivalence of this production test to data sheet limit at operating temperature range is established by
reliability testing.
Note 6: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term
storage at elevated temperatures is not recommended; the device can lose its write capability after 10
years at +125°C or 40 years at +85°C.
Note 7: All values are referred to VIHmin and VILmax levels.
Note 8: Applies to SDA, SCL, AD2, AD1, AD0.
Note 9: Guaranteed by simulation only, not production tested.
Note 10: I/O pins of the DS2460 do not obstruct the SDA and SCL lines if VCC is switched off.
Note 11: The DS2460 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
Note 13: A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
Note 14: CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I²C-Bus Specification v2.1 are allowed.
PIN DESCRIPTION
PIN NAME FUNCTION 1 AD0
2 AD1
3 AD2
I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave
address of the device, see Figure 5. GND Ground Reference
5 NC Not Connected SDA I²C Serial Data Input/Output; must be tied to VCC through a pullup resistor. SCL I²C Serial Clock Input; must be tied to VCC through a pullup resistor.
8 VCC Power Supply Input
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS2460. The DS2460 communicates with a host processor through its I²C bus interface in standard-mode or in
fast-mode. The logic state of three address pins determines the I²C slave address of the DS2460, allowing up to 8
devices to operate on the same bus segment without requiring a hub. For more information (including Figure 2)
Abridged Data Sheet DS2460
Figure 1. Block Diagram 64-bit Unique
Number
2-wire
Function
Control
SCL
SDA
E-Secret2
S-Secret
E-Secret3
112-Byte User
EEPROM
SHA-1
Engine
64-Byte Input
Buffer
MAC Output
Buffer
Command Buffer
and SHA-1
Engine Control
8-Byte EEPROM
Write Buffer
ADx
E-Secret1
DETAILED REGISTER DESCRIPTION For this section (including Figure 3) please refer to the full version of the data sheet.
DEVICE OPERATION The typical use of the DS2460 in an application involves writing, reading, running the SHA-1 engine, transferring
secrets and comparing MACs. All these activities are controlled through the I²C serial interface.
I²C Serial Communication Interface
General Characteristics The I²C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirec-
tional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both
lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to
perform the wired-AND function. Data on the I²C bus can be transferred at rates of up to 100kbps in the Standard-
mode, up to 400kbps in the Fast-mode. The DS2460 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” To be individually accessed, each device must have a slave address that does not conflict with other
devices on the bus.
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
Abridged Data Sheet DS2460
Slave Address The slave address to which the DS2460 responds is shown in Figure 5. The logic states at the address pins AD0,
AD1 and AD2 determine the value of the address bits A0, A2, and A4. The address pins allow the device to
respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode).
Figure 4. I²C Protocol Overview SCL
SDA678
ACK9128
MS-bitR/W
Slave Address
ACK
bit
Acknowledgment
from Receiver
ACK
bit
START
Condition
ACK
Repeated if more bytes
are transferred
STOP Condition
Repeated START
Condition
Idle
Figure 5. DS2460 Slave Address A5A4A3A2A1A00AD20AD10AD0R/W
7-Bit Slave Address
Most Signi-
ficant Bit
Determines
Read or Write
AD2, AD1, AD0
Pin States
I²C Definitions The following terminology is commonly used to describe I²C data transfers. The timing references are defined in
Figure 6.
Bus Idle or Not Busy Both, SDA and SCL, are inactive and in their logic HIGH states.
START Condition To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. A valid slave address must be
sent by the master and acknowledged by the slave before subsequent START conditions are recognized.
STOP Condition To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH. A valid slave address must be sent by the
master and acknowledged by the slave before subsequent STOP conditions are recognized.
Abridged Data Sheet DS2460
Repeated START Condition Repeated starts are commonly used for read accesses to select a specific data source or address to read from.
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START condition is generated the same way as a normal START
condition, but without leaving the bus idle after a STOP condition.
Data Valid With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 6).
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 6) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH
period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of
SCL and tSU:DAT before the rising edge of SCL).
Not Acknowledged by Slave A slave device may be unable to receive or transmit data, e.g., because it is busy performing a real-time function,
such as MAC computation or EEPROM write cycle. In this case the slave device will not acknowledge its slave
address and leave the SDA line HIGH.
A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later
the slave may refuse to accept data, e.g., because of an invalid command or access mode, or to signal a non-
matching MAC. In this case the slave device will not acknowledge any of the bytes that it refuses and will leave
SDA HIGH. In either case, after a slave has failed to acknowledge, the master first needs to generate a repeated
START condition or a STOP condition followed by a START condition to begin a new data transfer.
Not Acknowledged by Master At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the
master does not acknowledge the last byte that it has received from the slave. In response, the slave releases
SDA, allowing the master to generate the STOP condition.
Figure 6. I²C Timing Diagram SCL
SDA
tBUF
tHD:STA
tLOW
tR
tHD:DAT
tHIGH
tSU:DAT
tSU:STAtHD:STAtSP
tSU:STOSpike
Suppression
