DS14287 ,Real-Time Clock with NV RAM ControlPIN DESCRIPTION AD0-AD7 - Multiplexed Address/Data Bus NC - No Connection MOT - Bus Type Sele ..
DS14287+ ,Real-Time Clock with NV RAM ControlFEATURES PIN CONFIGURATIONS Direct Replacement for IBM AT TOP VIEW Computer Clock/Calendar Fun ..
DS1481S ,1-Wire Bus Master with OverdriveFEATURES PIN ASSIGNMENT• Provides a synchronous interface to Dallas Semicon-ductor 1–wire devices V ..
DS1481S+ ,1-Wire Bus Master with OverdriveFEATURES PIN CONFIGURATION Provides a synchronous interface to Dallas Vcc 1 1 ..
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DS1482S ,1-Wire Level Shifter and Line Driver with Load Sensorblock diagram. TXD is buffered and controls an N-channel transistor, whichdrives the 1-Wire pin I/O ..
DTC143ZCA ,Conductor Holdings Limited - Digital Transistor
DTC143ZE ,Pre-biased TransistorsMaximum ratings applied to the device are individual stress limit values (notnormal operating condi ..
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DTC143ZKA T146 , NPN 100mA 50V Digital Transistors
DTC143ZKA T146 , NPN 100mA 50V Digital Transistors
DS14285-DS14287
Real-Time Clock with NV RAM Control
FEATURES � Direct Replacement for IBM AT
Computer Clock/Calendar � Functionally Compatible with the
DS1285/DS1287 � Available as Chip (DS14285, DS14285S, or
DS14285Q) or Stand-Alone Module with
Embedded Lithium Battery and Crystal
(DS14287) � Automatic Backup Supply and Write
Protection to Make External SRAM
Nonvolatile � Counts Seconds, Minutes, Hours, Days,
Day of the Week, Date, Month, and Year
with Leap Year Compensation Valid Up
to 2100 � Binary or BCD Representation of Time,
Calendar, and Alarm � 12- or 24-Hour Clock with AM and PM in
12-Hour Mode � Daylight Saving Time Option � Multiplex Bus for Pin Efficiency � Interfaced with Software as 128 RAM
Locations
14 Bytes of Clock and Control Registers
114 Bytes of General Purpose RAM � Programmable Square-Wave Output
Signal � Bus-Compatible Interrupt Signals (IRQ) � Three Interrupts are Separately Software-
Maskable and Testable
Time-of-Day Alarm Once/Second to
Once/Day
Periodic Rates from 122µs to 500ms
End of Clock Update Cycle �
Optional Industrial Temperature Version
Available: DS14285 DIP, SO, and PLCC
PIN CONFIGURATIONS
DS14285/DS14287
Real-Time Clock with NV RAM
Control Control
PLCC AD0
AD1
AD2
AD3
AD4
AD5
CEI
VBAT
IRQ
RESET
GND
N.C.R/W
X2 X1 MOT VCCO VCC SQ
CE0
AD6N.C.AD7
GNDAS
N.C.
4 3 2 1 28 27 26
12 13 14 15 16 17 18
N.C.
AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
CEO
CEI
N.C.
IRQ
RESET
N.C.
R/W
N.C.
AD0
AD2
VCCO
Encapsulated Package
DS14287
DS14285
DIP/SO AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
CEI
VBAT
IRQ
RESET
DS
GND
R/W
AS
CS
AD0
AD2
SQW
CEO
VCCO
DS14
285 TOP VIEW
DS14285/DS14287
ORDERING INFORMATION
PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK*
DS14285 0°C to +70°C 5.0 24 DIP (0.600″) DS14285
DS14285+ 0°C to +70°C 5.0 24 DIP (0.600″) DS14285
DS14285N -40°C to +85°C 5.0 24 DIP (0.600″) DS14285N
DS14285N+ -40°C to +85°C 5.0 24 DIP (0.600″) DS14285N
DS14285Q 0°C to +70°C 5.0 28 PLCC DS14285Q
DS14285Q+ 0°C to +70°C 5.0 28 PLCC DS14285Q
DS14285QN -40°C to +85°C 5.0 28 PLCC DS14285QN
DS14285QN+ -40°C to +85°C 5.0 28 PLCC DS14285QN
DS14285S 0°C to +70°C 5.0 24 SO (0.300″) DS14285S
DS14285S+ 0°C to +70°C 5.0 24 SO (0.300″) DS14285S
DS14285SN -40°C to +85°C 5.0 24 SO (0.300″) DS14285SN
DS14285SN+ -40°C to +85°C 5.0 24 SO (0.300″) DS14285SN
DS14285SN/T&R -40°C to +85°C 5.0 24 SO (0.300″)/Tape & Reel DS14285SN
DS14285SN+T&R -40°C to +85°C 5.0 24 SO (0.300″)/Tape & Reel DS14285SN
DS14285S/T&R 0°C to +70°C 5.0 24 SO (0.300″)/Tape & Reel DS14285S
DS14285S+T&R 0°C to +70°C 5.0 24 SO (0.300″)/Tape & Reel DS14285S
DS14287 0°C to +70°C 5.0 24 EDIP (0.740″) DS14287
DS14287+ 0°C to +70°C 5.0 24 EDIP (0.740″) DS14287
+ Denotes a lead-free/RoHS-compliant device.
* A “+” anywhere on the top mark denotes a lead-free/RoHS-compliant device. An “N” denotes an industrial temperature grade device.
PIN DESCRIPTION AD0-AD7 - Multiplexed Address/Data Bus
NC - No Connection
MOT - Bus Type Select (DS14285Q only) - Chip Select
AS - Address Strobe W - Read/Write Input
DS - Data Strobe
RESET - Reset Input
IRQ - Interrupt Request Output
SQW - Square Wave Output
VCC - +5V Supply
GND - Ground
VCCO - RAM Power Supply Output
CEI - RAM Chip Enable In
CEO - RAM Chip Enable Out
X1, X2 - 32.768 kHz Crystal Connections
VBAT - +3V Battery Input
DS14285/DS14287
DETAILED DESCRIPTION The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287
clock function with the additional feature of providing nonvolatile control for an external SRAM.
Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt,
square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy
source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package.
The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external
energy source connected to the VBAT pin. A standard 32.768 kHz quartz crystal can be directly connected
to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load
capacitance (CL) of 6 pF. For more information on crystal selection and crystal layout considerations,
please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”
The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard
CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287
automatically write-protects the external SRAM and provides a VCC output sourced from its internal
battery.
For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when
shipped from the factory. This isolation is removed after the first application of VCC, allowing the lithium
cell to provide data retention to the clock, internal RAM, VCCO and CEO on subsequent power-downs.
Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell
through the VCCO and CEO pins.
OPERATION The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS14285/DS14287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input.
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE
bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts typical.
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287
since the bus change from address to data occurs during the internal RAM access time. Addresses must be
valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from
AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR
pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions
low in the case of Motorola timing or as RD transitions high in the case of Intel timing.
DS14285/DS14287
MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pull-down resistance of approximately 20 KΩ. This pin is
on the DS14285Q only.
AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.
DS (Data Strobe or Read Input) - For the DS14285Q the DS/RD pin has two modes of operation
depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is
selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data
Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In
write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is
connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read(RD).RD identifies
the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition
as the Output Enable (OE) signal on a typical memory.
The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus
timing mode.
W (Read/Write Input) - The R/W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level which indicates whether the current cycle is a
read or write. A read cycle is indicated with a high level on R/W while DS is high. A write cycle is
indicated when R/W is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/W signal is an active low signal called . In this mode the R/W pin has the same meaning as the Write Enable signal (WE) on generic
RAMs.
(Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the
DS14285/DS14287 to be accessed. CS must be kept in the active state during DS for Motorola timing
and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch
addresses but no access will occur. When VCC is below 4.25 volts, the DS14285/DS14287 internally
inhibits access cycles by internally disabling the CS input. This action protects both the real time clock
data and RAM data during power outages.
IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS14285/DS14287 that
can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit
causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the
processor program normally reads the C register. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
DS14285/DS14287
RESET (Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the
RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
that RESET is held low is dependent on the application. However, if RESET is used on power-up, the
time RESET is low should exceed 200 ms to make sure that the internal timer that controls the
DS14285/DS14287 on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the
following occurs:
A. Periodic Interrupt Enable (PEI) bit is cleared to 0.
B. Alarm Interrupt Enable (AIE) bit is cleared to 0.
C. Update Ended Interrupt Flag (UF) bit is cleared to 0.
D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E. Periodic Interrupt Flag (PF) bit is cleared to 0.
F. The device is not accessible until RESET is returned high.
G. Alarm Interrupt Flag (AF) bit is cleared to 0.
H. IRQ pin is in the high impedance state.
I. Square Wave Output Enable (SQWE) bit is cleared to 0.
J. Update Ended Interrupt Enable (UIE) is cleared to 0.
K. CEO is driven high.
In a typical application RESET can be connected to VCC. This connection will allow the DS14287 to go in
and out of power fail without affecting any of the control registers.
CEI (External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external
RAM. CEI is internally pulled up with a 50kΩ resistor.
CEO (External RAM Chip Enable Output, active low) - When VCC is greater than 4.25 volts (typical), CEO will reflect CEI provided the RESET is at a logic high. When VCC is less than 4.25 volts (typical),
CEO will be forced to an inactive level regardless of CEI.
VCCO (External RAM Power Supply Output) - VCCO provides the higher of VCC or VBAT through an internal switch to power an external RAM.
DS14285 Only
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is
connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1
and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with
ground and that high frequency signals be kept away from the crystal area. For more information on
crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
VBAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down
DS14285/DS14287
The battery should be connected directly to the VBAT pin. A diode must not be placed in series with the
battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current
protection circuitry is provided internal to the device and has passed the requirements of Underwriters
Laboratories for UL listing.
Figure 1. DS14285/DS14287 Block Diagram DS14285/DS14287
POWER-DOWN/POWER-UP CONSIDERATIONS The real time clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the
DS14285/DS14287 and reaches a level of greater than 4.25 volts (typical), the device becomes accessible
after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see
Register A). This time period allows the system to stabilize after power is applied. When VCC falls below
4.25 volts (typical), the chip select input is internally forced to an inactive level regardless of the value of at the input pin. The DS14285/DS14287 is, therefore, write-protected. When the DS14285/DS14287
is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When
VCC falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal
lithium energy source supplies power to the Real-time Clock and the RAM memory.
An external SRAM can be made nonvolatile by using the VCCO and SRAM chip enable pins (see Figure
1). Nonvolatile control of the external SRAM is analogous to that of the real time clock registers. When
VCC slews down during a power fail, CEO is driven to an inactive level regardless CEI. This write
protection occurs when VCC is less than 4.25 volts (typical).
During power up, when VCC reaches a level of greater than 4.25 volts (typical), CEO will reflect CEI
after 200 ms. During power-valid operation, the CEI input is passed to the CEO output with a
propagation delay of less than 10 ns.
When VCC is above a level of approximately 3V, the external SRAM will be powered by VCC through the
VCCO pin. When VCC is below a level of approximately 3V, the external SRAM will be powered by the
internal lithium cell through the VCCO pin. An internal comparator and switch determine whether VCCO is
powered by VCC or the internal lithium cell.
When the device is in battery backup mode, the energy source connected to the VBAT pin in the case of
the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an
extended period of time. The amount of time that the lithium cell can supply power to the external SRAM
is a function of the data retention current of the SRAM. The capacity of the lithium cell that is
encapsulated within the DS14287 module is 130 mAh. If an SRAM with a data retention current of less
than 1 µA is used and the oscillator current is 300 nA (typical), the cumulative data retention time is
calculated at more than 11 years.
DS14285/DS14287
RTC ADDRESS MAP The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes
of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which
are used for control and status. All 128 bytes can be directly written or read except for the following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
The contents of four registers (A,B,C, and D) are described in the “Registers” section.
Figure 2. DS14285/DS14287 Address Map
TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10
time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before
writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10
time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written to
DS14285/DS14287
24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is
selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar,
and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are
advanced by 1 second and checked for an alarm condition. If a read of the time and calendar data occurs
during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability
of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect
time and calendar reads are covered later in this text.
The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate
hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day
if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of
the 3 alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The 2 most significant
bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour
when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with
“don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes
create an interrupt every second.
Table 1. Time, Calendar, and Alarm Data Modes
RANGE ADDRESS
LOCATION FUNCTION DECIMAL
RANGE BINARY DATA MODE BCD DATA MODE 0 Seconds 0-59 00-3B 00-59
1 Seconds Alarm 0-59 00-3B 00-59
2 Minutes 0-59 00-3B 00-59
3 Minutes Alarm 0-59 00-3B 00-59
Hours-12-hr Mode 1-12 01-0C AM, 81-8C PM 01-12AM, 81-92PM 4
Hours-24-hr Mode 0-23 00-17 00-23
Hours Alarm-12-hr 1-12 01-0C AM, 81-8C PM 01-12AM, 81-92PM 5
Hours Alarm-24-hr 0-23 00-17 00-23 Day of the Week
Sunday = 1
1-7 01-07 01-07 Date of the Month 1-31 01-1F 01-31
8 Month 1-12 01-0C 01-12
9 Year 0-99 00-63 00-99
DS14285/DS14287
CONTROL REGISTERS The DS14285/DS14287 has four control registers that are accessible at all times, even during the update
cycle.
REGISTER A
MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 µs.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The
UIP bit is read-only and is not affected by RESET. Writing the SET bit in Register B to a 1 inhibits any
update transfer and clears the UIP status bit.
DV0, DV1, DV2 - These 3 bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep
time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update
will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;
3. Enable both at the same time and the same rate; or
4. Enable neither.
Table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS
bits. These 4 read/write bits are not affected by RESET.
DS14285/DS14287
REGISTER B
MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SET PIE AIE UIE SQWE DM 24/12 DSE
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit that is not modified by RESET or internal functions
of the DS14285/DS14287.
PIE - The periodic interrupt enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are
generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the
PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is
still set at the periodic rate. PIE is not modified by any internal DS14285/DS14287 functions, but is
cleared to 0 on RESET.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm Flag (AF) bit in register C to assert IRQ. An alarm interrupt occurs for each second that the 3 time bytes
equal the 3 alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is
set to 0, the AF bit does not initiate the IRQ signal. The RESET pin clears AIE to 0. The internal
functions of the DS14285/DS14287 do not affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF) bit in Register C to assert IRQ. The RESET pin going low or the SET bit going high clears to UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency set by the rate-selection bits RS3 through RS0 is driven out on a SQW pin. When the SQWE bit is set to
0, the SQW pin is held low; the state of SQWE is cleared by the RESET pin. SQWE is a read/write bit.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions or RESET. A one in DM signifies binary data while a 0 in DM
specifies Binary Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions of RESET.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions or
RESET.
DS14285/DS14287
REGISTER C
MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IRQF PF AF UF 0 0 0 0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true: PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
That is, IRQF = PF • PIE + AF • AIE + UF • UIE.
Any time the IRQF bit is a 1, the IRQ pin is driven low. All flag bits are cleared after Register C is read
by the program or when the RESET pin is low.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set
the IRQF bit. The PF bit is cleared by a RESET or a software read of Register C.
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a 1, the IRQ pin will go low and a one will appear in the IRQF bit. A RESET or a
read of Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to 1, the 1 in UF causes the IRQF bit to be a 1 which will assert the IRQ pin. UF is cleared by reading
Register C or a RESET.
BIT 0 THROUGH BIT 3 - These are unused bits of the status Register C. These bits always read 0 and cannot be written.
REGISTER D MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VRT 0 0 0 0 0 0 0
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the internal battery (the battery connected to the VBAT pin in the case of the DS14285S, DS14285, and the DS14285Q). This bit is not
writable and should always be a 1 when read. If a 0 is ever present, an exhausted internal lithium energy
source is indicated and both the contents of the RTC data and RAM data are questionable. This bit is
unaffected by RESET.
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
DS14285/DS14287
NONVOLATILE RAM The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS14285/DS14287. They can be used by the processor program as nonvolatile memory and are fully
available during the update cycle.
The DS14285/DS14287 can also provide additional nonvolatile RAM. This is accomplished through the
use of its internal lithium cell in the case of the DS14287 (or the energy source connected to the VBAT pin
in the case of the DS14285) and battery-backup controller to make a standard CMOS SRAM nonvolatile
during power-fail conditions. During power-fail, the DS14285/DS14287 automatically write-protects the
external SRAM and provides a VCC output sourced from the internal lithium cell. The interface between
the DS14285/DS14287 and an external SRAM is illustrated in Figure 3.
Figure 3. External SRAM Interface to the DS14285/DS14287 RTC
INTERRUPTS The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500 ms to 122 µs. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when
the event occurs. A 0 in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set
at an active level, although the interrupt initiating the event may have occurred much earlier. As a result,
there are cases where the program should clear such earlier initiated interrupts before first enabling new
interrupts. When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag
bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used
in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit
