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DS1305E+T&R-DS1305EN+
Serial Alarm Real-Time Clock
FEATURESReal-time clock (RTC) counts seconds,minutes, hours, date of the month, month,
day of the week, and year with leap-year
compensation valid up to 210096-byte, battery-backed NV RAM for data
storageTwo time-of-day alarms, programmable on
combination of seconds, minutes, hours, and
day of the weekSerial interface supports Motorola SPI™
(serial peripheral interface) serial data portsor standard 3-wire interfaceBurst mode for reading/writing successive
addresses in clock/RAMDual-power supply pins for primary and
backup power suppliesOptional trickle charge output to backup
supply2.0V to 5.5V operationOptional industrial temperature range:
-��C to +85�CAvailable in space-efficient, 20-pin TSSOP
packageUnderwriters Laboratory (UL) recognized
ORDERING INFORMATIONDS1305 16-Pin DIP (300mil)
DS1305N 16-Pin DIP (Industrial)
DS1305E 20-Pin TSSOP (173mil)
DS1305EN 20-Pin TSSOP (Industrial)
PIN ASSIGNMENT
DS1305
Serial Alarm Real-Time Clock
Package dimension information can be found at:http:///TechSupport/DallasPackInfo.htm
DS1305
PIN DESCRIPTION
VCC1- Primary Power Supply
VCC2 - Backup Power Supply
VBAT - +3V Battery Input
VCCIF - Interface Logic Power-Supply Input
GND - GroundX1, X2 - 32,768kHz Crystal Connection
INT0 - Interrupt 0 Output
INT1 - Interrupt 1 Output
SDI - Serial Data In
SDO - Serial Data Out
CE - Chip Enable
SCLK - Serial ClockSERMODE - Serial Interface Mode - Power-Fail Output
DESCRIPTION
The DS1305 serial alarm real-time clock provides a full binary coded decimal (BCD) clock calendar that
is accessed by a simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date,
month, and year information. The end of the month date is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour
format with AM/PM indicator. In addition, 96 bytes of NV RAM are provided for data storage.
An interface logic power-supply input pin (VCCIF) allows the DS1305 to drive SDO and PFpins to a level
that is compatible with the interface logic. This allows an easy interface to 3V logic in mixed supply
systems.
The DS1305 offers dual-power supplies as well as a battery input pin. The dual power supplies support aprogrammable trickle charge circuit that allows a rechargeable energy source (such as a super cap or
rechargeable battery) to be used for a backup supply. The VBAT pin allows the device to be backed up by
a non-rechargeable battery. The DS1305 is fully operational from 2.0V to 5.5V.
Two programmable time-of-day alarms are provided by the DS1305. Each alarm can generate aninterrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. The time-of-
day alarms can be programmed to assert two different interrupt outputs or to assert one common interrupt
output. Both interrupt outputs operate when the device is powered by VCC1, VCC2, or VBAT.
The DS1305 supports a direct interface to SPI serial data ports or standard 3-wire interface. A
straightforward address and data format is implemented in which data transfers can occur 1 byte at a time
or in multiple-byte-burst mode.
DS1305
OPERATION
The block diagram in Figure 1 shows the main elements of the serial alarm RTC. The following
paragraphs describe the function of each pin.
Figure 1. BLOCK DIAGRAM
SIGNAL DESCRIPTIONS
VCC1 – DC power is provided to the device on this pin. VCC1 is the primary power supply.
VCC2 – This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
energy source is connected to this pin.
VBAT – Battery input for any standard 3V lithium cell or other energy source. UL recognized to ensureagainst reverse charging current when used in conjunction with a lithium battery.
See “Conditions of Acceptability” at http:///TechSupport/QA/ntrl.htm.
VCCIF (Interface Logic Power-Supply Input) – The VCCIF pin allows the DS1305 to drive SDO and PF
output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3V
logic in mixed supply systems. This pin is physically connected to the source connection of the p-channel
transistors in the output buffers of the SDO and PF pins.
SERMODE (Serial Interface Mode Input) – The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, SPI communication is selected.
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.
DS1305
SDI (Serial Data Input) – When SPI communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).
SDO (Serial Data Output) – When SPI communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI and
SDO pins function as a single I/O pin when tied together).
CE (Chip Enable) – The chip enable signal must be asserted high during a read or a write for both 3-wire and SPI communication. This pin has an internal 55k pulldown resistor (typical).
INT0(Interrupt 0 Output) – The INT0pin is an active low output of the DS1305 that can be used as an
interrupt input to a processor. The INT0pin can be programmed to be asserted by only Alarm 0 or can be
programmed to be asserted by either Alarm 0 or Alarm 1. The INT0pin remains low as long as the status
bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0pin operates
when the DS1305 is powered by VCC1, VCC2, or VBAT. The INT0pin is an open drain output and requires
an external pullup resistor.
INT1(Interrupt 1 Output) – The INT1pin is an active-low output of the DS1305 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1 only. The
INT1 pin remains low as long as the status bit causing the interrupt is present and the corresponding
interrupt enable bit is set. The INT1 pin operates when the DS1305 is powered by VCC1, VCC2, or VBAT.
The INT1 pin is an open-drain output and requires an external pullup resistor.
Both INT0and INT1are open-drain outputs. The two interrupts and the internal clock continue to run
regardless of the level of VCC (as long as a power source is present). (Power-Fail Output) – The PF pin is used to indicate loss of the primary power supply (VCC1).
When VCC1 is less than VCC2 or is less than VBAT, the PF pin is driven low.
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6pF. For more information on crystal
selection and crystal layout considerations, refer to Application Note 58, “Crystal Considerations withDallas Real-Time Clocks.” The DS1305 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
DS1305
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application
Note 58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
CLOCK, CALENDAR, AND ALARM
The time and calendar information is obtained by reading the appropriate register bytes. The RTC
registers and user RAM are illustrated in Figure 2. The time, calendar, and alarm are set or initialized by
writing the appropriate register bytes. Note that some bits are set to 0. These bits always read 0 regardlessof how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved.
These registers always read 0 regardless of how they are written. The contents of the time, calendar, and
alarm registers are in the BCD format.
Except where otherwise noted, the initial power on state of all registers is not defined. Therefore, it isimportant to enable the oscillator (EOSC = 0) and disable write protect (WP = 0) during initial
configuration.
WRITING TO THE CLOCK REGISTERS
The internal time and date registers continue to increment during write operations. However, the
countdown chain is reset when the seconds register is written. Writing the time and date registers withinone second after writing the seconds register ensures consistent data.
Terminating a write before the last bit is sent aborts the write for that byte.
READING FROM THE CLOCK REGISTERS
Buffers are used to copy the time and date register at the beginning of a read. When reading in burst
mode, the user copy is static while the internal registers continue to increment.
DS1305
Figure 2. RTC REGISTERS AND ADDRESS MAP
Note: Range for alarm registers does not include mask’m’ bits.
The DS1305 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the
AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23
hours).
The DS1305 contains two time-of-day alarms. Time-of-day Alarm 0 can be set by writing to registers 87h
to 8Ah. Time-of-day Alarm 1 can be set by writing to registers 8Bh to 8Eh. The alarms can be
programmed (by the INTCN bit of the control register) to operate in two different modes; each alarm can
drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each
of the time-of-day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time-of-day alarm only occurs once per week when the values stored in timekeeping registers 00h to 03h
match the values stored in the time-of-day alarm registers. An alarm is generated every day when bit 7 of
the day alarm register is set to a logic 1. An alarm is generated every hour when bit 7 of the day and hour
alarm registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day,
hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and secondsalarm registers is set to a logic 1, alarm occurs every second.
DS1305
During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding
clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If
the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated.
Table 1. TIME-OF-DAY ALARM MASK BITS
SPECIAL PURPOSE REGISTERS
The DS1305 has three additional registers (control register, status register, and trickle charger register)that control the RTC, interrupts, and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
EOSC (Enable Oscillator) – This bit when set to logic 0 startS the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1305 is placed into a low-power standby mode with a current
drain of less than 100nA when power is supplied by VBAT or VCC2. The initial power-on state is not
defined.
WP (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, 2, and 7 of the
control register. Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should
be cleared before attempting to write to the device.
INTCN (Interrupt Control) – This bit controls the relationship between the two time-of-day alarms and
the interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping
registers and the Alarm 0 registers activates the INT0 pin (provided that the alarm is enabled) and a
match between the timekeeping registers and the Alarm 1 registers activate the INT1 pin (provided that
the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping registers
and either Alarm 0 or Alarm 1 activate the INT0 pin (provided that the alarms are enabled). INT1 has no
function when INTCN is set to a logic 0.
AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag
(IRQF0) bit in the status register to assert INT0. When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag
(IRQF1) bit in the status register to assert INT1 (when INTCN = 1) or to assert INT0 (when INTCN = 0).
DS1305
STATUS REGISTER (READ 10H)
IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin goes low. IRQF0 is
cleared when the address pointer goes to any of the Alarm 0 registers during a read or write.
IRQF1 (Interrupt 1 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current
time has matched the Alarm 1 registers. This flag can be used to generate an interrupt on either INT0 or
INT1 depending on the status of the INTCN bit in the control register. If the INTCN bit is set to a logic 1
and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT1 pin goes low. If the INTCN bit is set
to a logic 0 and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT0 pin goes low. IRQF1 is
cleared when the address pointer goes to any of the Alarm 1 registers during a read or write.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
This register controls the trickle charge characteristics of the DS1305. The simplified schematic of Figure
3 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4–7)
control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables
the trickle charger. All other patterns disable the trickle charger. On the initial application of power, theDS1305 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2–3) select whether
one diode or two diodes are connected between VCC1 and VCC2. The resistor select (RS) bits select the
resistor that is connected between VCC1 and VCC2. The resistor and diodes are selected by the RS and DS
bits, as shown in Table 2.
Figure 3. PROGRAMMABLE TRICKLE CHARGER
DS1305
Table 2. TRICKLE CHARGER RESISTOR AND DIODE SELECT
The user determines diode and resistor selection according to the maximum current desired for battery or
super cap charging. The maximum charging current can be calculated as illustrated in the followingexample. Assume that a system power supply of 5V is applied to VCC1 and a super cap is connected to
VCC2. Also assume that the trickle charger has been enabled with 1 diode and resister R1 between VCC1
and VCC2. The maximum current IMAX would, therefore, be calculated as follows:
IMAX = (5.0V - diode drop) / R1 � (5.0V - 0.7V) / 2k�� 2.2mA
As the super cap charges, the voltage drop between VCC1 and VCC2 decreases and, therefore, the charge
current decreases.
POWER CONTROL
Power is provided through the VCC1, VCC2, and VBAT pins. Three different power-supply configurationsare illustrated in Figure 4. Configuration 1 shows the DS1305 being backed up by a nonrechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected to
VCC1 and VCC2 is grounded. The DS1305 is write-protected if VCC1 is less than VBAT. The DS1305 is fully
accessible when VCC1 is greater than VBAT + 0.2V.
Configuration 2 illustrates the DS1305 being backed up by a rechargeable energy source. In this case, the
VBAT pin is grounded, VCC1 is connected to the primary power supply, and VCC2 is connected to the
secondary supply (the rechargeable energy source). The DS1305 operates from the larger of VCC1 or
VCC2. When VCC1 is greater than VCC2 + 0.2V (typical), VCC1 powers the DS1305. When VCC1 is less than
VCC2, VCC2 powers the DS1305. The DS1305 does not write-protect itself in this configuration.
Configuration 3 shows the DS1305 in battery operate mode where the device is powered only by a single
battery. In this case, the VCC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin.
Only these three configurations are allowed. Unused supply pins must be grounded.
DS1305
Figure 4. POWER SUPPLY CONFIGURATIONS
Configuration 1: Backup Supply is a Nonrechargeable Lithium Battery
Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor
Configuration 3: Battery Operate Mode

Partno	Mfg	Dc	Qty	Available	Descript
DS1305E+T&R \|DS1305ET&R	MAXIM	N/a	15000	avai	Serial Alarm Real-Time Clock
DS1305EN+ \|DS1305EN	DALLA	N/a	518	avai	Serial Alarm Real-Time Clock