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DS12887+ |DS12887DALLASN/a627avaiReal-Time Clocks
DS12887A+ |DS12887AMAXIMN/a60avaiReal-Time Clocks
DS12887A+ |DS12887ADALLASN/a365avaiReal-Time Clocks
DS12C887+ |DS12C887N/a27avaiReal-Time Clocks


DS12887+ ,Real-Time ClocksELECTRICAL CHARACTERISTICS(V = 0V, V = 3.0V, T = over the operating range, unless otherwise noted.) ..
DS12887A ,Real time clockFEATURES PIN ASSIGNMENT (Top View) Drop-in replacement for IBM AT computerclock/calendarMOT1 24 VC ..
DS12887A ,Real time clockDS12887AReal-Time Clock
DS12887A ,Real time clockDS12887AReal-Time Clock
DS12887A ,Real time clockPIN DESCRIPTION Multiplex bus for pin efficiency AD0–AD7 - Multiplexed Address/Data Bus Interface ..
DS12887A ,Real time clockPIN DESCRIPTION Multiplex bus for pin efficiency AD0–AD7 - Multiplexed Address/Data Bus Interface ..
DTC114WCA ,Conductor Holdings Limited - Digital Transistor
DTC114WE , 100mA / 50V Digital transistors (with built-in resistors)
DTC114WUA , 100mA / 50V Digital transistors (with built-in resistors)
DTC114YCA ,Conductor Holdings Limited - Digital Transistor
DTC114YE TL , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DTC114YET1 ,Bias Resistor Transistor3DTC114YEMINIMUM RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONSSurface mount board layout ..


DS12887+-DS12887A+-DS12C887+
Real-Time Clocks
General Description
The DS12885, DS12887, and DS12C887 real-time
clocks (RTCs) are designed to be direct replacements
for the DS1285 and DS1287. The devices provide a
real-time clock/calendar, one time-of-day alarm, three
maskable interrupts with a common interrupt output, a
programmable square wave, and 114 bytes of battery-
backed static RAM (113 bytes in the DS12C887 and
DS12C887A). The DS12887 integrates a quartz crystal
and lithium energy source into a 24-pin encapsulated
DIP package. The DS12C887 adds a century byte at
address 32h. For all devices, the date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including correction for leap years. The
devices also operate in either 24-hour or
12-hour format with an AM/PM indicator. A precision
temperature-compensated circuit monitors the status of
VCC. If a primary power failure is detected, the device
automatically switches to a backup supply. A lithium
coin-cell battery can be connected to the VBATinput
pin on the DS12885 to maintain time and date operation
when primary power is absent. The device is accessed
through a multiplexed byte-wide interface, which sup-
ports both Intel and Motorola modes.
Applications

Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
Features
Drop-In Replacement for IBM AT Computer
Clock/Calendar
RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap Year Compensation
Through 2099
Binary or BCD Time Representation12-Hour or 24-Hour Clock with AM and PM in
12-Hour Mode
Daylight Saving Time OptionSelectable Intel or Motorola Bus TimingInterfaced with Software as 128 RAM Locations14 Bytes of Clock and Control Registers114 Bytes of General-Purpose, Battery-Backed
RAM (113 Bytes in the DS12C887 and
DS12C887A)
RAM Clear Function (DS12885, DS12887A, and
DS12C887A)
Interrupt Output with Three Independently
Maskable Interrupt Flags
Time-of-Day Alarm Once Per Second to Once
Per Day
Periodic Rates from 122µs to 500msEnd-of-Clock Update Cycle FlagProgrammable Square-Wave OutputAutomatic Power-Fail Detect and Switch CircuitryOptional 28-Pin PLCC Surface Mount Package or
32-Pin TQFP (DS12885)
Optional Encapsulated DIP (EDIP) Package with
Integrated Crystal and Battery (DS12887,
DS12887A, DS12C887, DS12C887A)
Optional Industrial Temperature Range AvailableUnderwriters Laboratory (UL) Recognized
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks

DS12885DS83C520
R/W
GNDX1
VCC
VCC
CRYSTAL
VBAT
AD(0–7)SQW
RESET
IRQ
RCLR
MOT
Typical Operating Circuit

19-5213; Rev 4; 4/10
Pin Configurations and Ordering Information appear at end of data sheet.
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCPin Relative to Ground.....-0.3V to +6.0V
Operating Temperature Range ...................................................
Commercial (noncondensing).............................0°C to +70°C
Operating Temperature Range ...................................................
Industrial (noncondensing)...............................-40°C to +85°C
Storage Temperature Range
EDIP..................................................................-40°C to +85°C
PDIP, SO, PLCC, TQFP..................................-55°C to +125°C
Lead Temperature (soldering, 10s).................................+260°C
(Note:EDIP is hand or wave-soldered only.)
Soldering Temperature (reflow)
PDIP, SO, PLCC............................................................+260°C
TQFP.............................................................................+245°C
DC ELECTRICAL CHARACTERISTICS

(VCC = +4.5V to +5.5V, TA= over the operating range, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Supply VoltageVCC(Note 3)4.55.5V
VBAT Input VoltageVBAT(Note 3)2.54.0V
Input Logic 1VIH(Note 3)2.2VCC +
0.3V
Input Logic 0VIL(Note 3)-0.3+0.8V
VCC Power-Supply CurrentICC1(Note 4)15mA
VCC Standby CurrentICCS(Note 5)mA
Input LeakageIIL-1.0+1.0µA
I/O LeakageIOL(Note 6)-1.0+1.0µA
Input CurrentIMOT(Note 7)-1.0+500µA
Output at 2.4VIOH(Note 3)-1.0mA
Output at 0.4VIOL(Note 3)4.0mA
Power-Fail VoltageVPF(Note 3)4.04.254.5V
VRT Trip PointVRTTRIP1.3V
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
DC ELECTRICAL CHARACTERISTICS

(VCC= 0V, VBAT= 3.0V, TA= over the operating range, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

VBAT Current (OSC On);
TA = +25°C, VBACKUP = 3.0VIBAT(Note 8)500nA
VBAT Current (Oscillator Off)IBATDR(Note 8)100nA
AC ELECTRICAL CHARACTERISTICS

(VCC= 4.5V to 5.5V, TA= over the operating range.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Cycle TimetCYC385DCns
Pulse Width, DS Low or R/W HighPWEL150ns
Pulse Width, DS High or R/W LowPWEH125ns
Input Rise and FalltR, tF30ns
R/W Hold TimetRWH10ns
R/W Setup Time Before DS/EtRWS50ns
Chip-Select Setup Time Before
DS or R/WtCS20ns
Chip-Select Hold TimetCH0ns
Read-Data Hold TimetDHR1080ns
Write-Data Hold TimetDHW0ns
Address Valid Time to AS FalltASL30ns
Address Hold Time to AS FalltAHL10ns
Delay Time DS/E to AS RisetASD20ns
Pulse Width AS HighPWASH60ns
Delay Time, AS to DS/E RisetASED40ns
Output Data Delay Time from DS
or R/WtDDR20120ns
Data Setup TimetDSW100ns
Reset Pulse WidthtRWL5µs
IRQ Release from DStIRDS2µs
IRQ Release from RESETtIRR2µs
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks

PWASH
PWEL
tASED
tCYC
tRWS
tCS
tRWH
tCH
PWEH
tASD
AD0–AD7
READ
R/W
AD0–AD7
WRITE
tDHW
tDHR
tDDR
tAHLtASL
tDSW
Motorola Bus Read/Write Timing
Intel Bus Write Timing

PWASH
PWELPWEH
tCS
tAHLtASLtDSWtDHW
tCH
tASD
tASD
tCYC
R/W
AD0–AD7
WRITE
tASED
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks

tCS
tAHLtASL
tCYC
PWASH
PWELPWEH
R/W
AD0–AD7
tASD
tASD
tASED
tDDRtDHR
tCH
Intel Bus Read Timing

tRWL
tIRR
tIRDS
RESET
IRQ
IRQRelease Delay Timing

OUTPUTS
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZEDRECOGNIZED
VALID
VCC
VPF(MAX)
VPF(MIN)
tRPU
tDR
Power-Up/Power-Down Timing
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
POWER-UP/POWER-DOWN CHARACTERISTICS

(TA= -40°C to +85°C) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Recovery at Power-UptRPU20200ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)tF300µs
VCC Rise Time; VPF(MIN) to
VPF(MAX)tR0µs
CAPACITANCE

(TA= +25°C) (Note 9)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Capacitance on All Input Pins
Except X1 and X2CIN5pF
Capacitance on IRQ, SQW, and
DQ PinsCIO7pF
DATA RETENTION

(TA= +25°C)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Expected Data RetentiontDR10yearsTESTCONDITIONS
PARAMETERTEST CONDITIONS

Input Pulse Levels0 to 3.0V
Output Load Including Scope and Jig50pF + 1TTL Gate
Input and Output Timing Measurement Reference LevelsInput/Output: VIL maximum and VIH minimum
Input-Pulse Rise and Fall Times5ns
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1:
RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage.
Note 2:
Limits at -40°C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
All outputs are open.
Note 5:
Specified with CS= DS = R/W= RESET= VCC; MOT, AS, AD0–AD7 = 0; VBACKUPopen.
Note 6:
Applies to the AD0 to AD7 pins, the IRQpin, and the SQW pin when each is in a high-impedance state.
Note 7:
The MOT pin has an internal 20kΩpulldown.
Note 8:
Measured with a 32.768kHz crystal attached to X1 and X2.
Note 9:
Guaranteed by design. Not production tested.
Note 10:
Measured with a 50pF capacitance load.
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
Typical Operating Characteristics

(VCC= +5.0V, TA= +25°C, unless otherwise noted.)
OSCILLATOR FREQUENCY
vs. VCC

DS12885 toc02
VCC (V)
FREQUENCY (Hz)
IBAT1 vs. VBAT
vs. TEMPERATURE
DS12885 toc01
VBAT (V)
BAT
(nA)
VCC = 0V+85°C
+25°C
0°C
-40°C
+70°C
+40°C
POWER
CONTROL
GND
OSC
BUS
INTERFACE
VCC
RESET
R/W
MOT
AD0–AD7
DIVIDE
BY 8
DIVIDE
BY 64
DIVIDE
BY 64
16:1 MUX
SQUARE-
WAVE
GENERATOR
REGISTERS A, B, C, D
CLOCK/CALENDAR AND
ALARM REGISTERS
USER RAM
114 BYTES
CLOCK/CALENDAR
UPDATE LOGIC
IRQ
SQW
IRQ
GENERATOR
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
VBAT
RLCR
DS12885
Functional Diagram
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
Pin Description
PIN
SO,
PDIPEDIPPLCCTQFPNAMEFUNCTION
1229MOT
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or
left disconnected, Intel bus timing is selected. The pin has an internal pulldown
resistor.330X1431X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a 6pF specified load
capacitance (CL). Pin X1 is the input to the oscillator and can optionally be
connected to an external 32.768kHz oscillator. The output of the internal oscillator,
pin X2, is left unconnected if an external oscillator is connected to pin X1.
4–114–115–10,
12, 14
1, 2, 3,
5, 7, 8,
9, 11
AD0–
AD7
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during
the first portion of the bus cycle and latched into the device by the falling edge of
AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising
edge of R/W (Intel timing). In a read cycle, the device outputs data during the
latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for
Intel timing). The read cycle is terminated and the bus returns to a high-
impedance state as DS transitions low in the case of Motorola timing or as DS
transitions high in the case of Intel timing.
12, 161215, 2012, 17GNDGround131613CS
Active-Low Chip-Select Input. The chip-select signal must be asserted low for a
bus cycle in the device to be accessed. CS must be kept in the active state during
DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles
that take place without asserting CS will latch addresses, but no access occurs.
When VCC is below VPF volts, the device inhibits access by internally disabling the
CS input. This action protects the RTC data and the RAM data during power
outages.141714AS
Address Strobe Input. A positive-going address-strobe pulse serves to
demultiplex the bus. The falling edge of AS causes the address to be latched
within the device. The next rising edge that occurs on the AS bus clears the
address regardless of whether CS is asserted. An address strobe must
immediately precede each write or read access. If a write or read is performed
with CS deasserted, another address strobe must be performed prior to a read or
write access with CS asserted.151916R/W
Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level that indicates whether the
current cycle is a read or write. A read cycle is indicated with a high level on R/W
while DS is high. A write cycle is indicated when R/W is low during DS. When the
MOT pin is connected to GND for Intel timing, the R/W signal is an active-low
signal. In this mode, the R/W pin operates in a similar fashion as the write-enable
signal (WE) on generic RAMs. Data are latched on the rising edge of the signal.
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Pin Description (continued)
PIN
SO,
PDIPEDIPPLCCTQFPNAMEFUNCTION

2, 3,
16, 20,
21, 22
1, 11,
13, 18,
4, 6, 10,
15, 20,
23, 25,
27, 32
N.C.No Connection. This pin should remain unconnected. Pin 21 is RCLR for the
DS12887A/DS12C887A. On the EDIP, these pins are missing by design.172118DSata S tr ob e or Read Inp ut. The D S p i n has tw o m od es of op er ati on d ep end i ng on
the l evel of the M O T p i n. W hen the M O T p i n i s connected to V C C , M otor ol a b us
ti m i ng i s sel ected . In thi s m od e, D S i s a p osi ti ve p ul se d ur i ng the l atter p or ti on of theus cycl e and i s cal l ed d ata str ob e. D ur i ng r ead cycl es, D S si g ni fi es the ti m e that the
device i s to d r i ve the b i d i r ecti onal b us. In w r i te cycl es, the tr ai l i ng ed g e of D S causes
the device to l atch the w r i tten d ata. W hen the M O T p i n i s connected to GN D , Intel us ti m i ng i s sel ected . D S i d enti fi es the ti m e p er i od w hen the device d r i ves the b usi th r ead d ata. In thi s m od e, the D S p i n op er ates i n a si m i l ar fashi on as the outp ut-
enab l e ( O E ) si g nal on a g ener i c RAM .182219RESET
Active-Low Reset Input. The RESET pin has no effect on the clock, calendar, or
RAM. On power-up, the RESET pin can be held low for a time to allow the power
supply to stabilize. The amount of time that RESET is held low is dependent on the
application. However, if RESET is used on power-up, the time RESET is low should
exceed 200ms to ensure that the internal timer that controls the device on power-
up has timed out. When RESET is low and VCC is above VPF, the following occurs:
A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H. IRQ pin is in the high-impedance state.
I. The device is not accessible until RESET is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application, RESET can be connected to VCC. This connection allows
the device to go in and out of power fail without affecting any of the control
registers.
Real-Time Clocks
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
Pin Description (continued)
PIN
SO,
PDIPEDIPPLCCTQFPNAMEFUNCTION
192321IRQ
Active-Low Interrupt Request Output. The IRQ pin is an active-low output of the
device that can be used as an interrupt input to a processor. The IRQ output
remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. The processor program normally
reads the C register to clear the IRQ pin. The RESET pin also clears pending
interrupts. When no interrupt conditions are present, the IRQ level is in the high-
impedance state. Multiple interrupting devices can be connected to an IRQ
bus, provided that they are all open drain. The IRQ pin is an open-drain output
and requires an external pullup resistor to VCC.—2422VBAT
Connection for a Primary Battery. (DS12885 Only.) Battery voltage must be held
between the minimum and maximum limits for proper operation. If a backup
supply is not supplied, VBAT must be grounded. Connect the battery directly to
the VBAT pin. Diodes in series between the VBAT pin and the battery may
prevent proper operation. UL recognized to ensure against reverse charging
when used with a lithium battery.
(DS12887A/
DS12C887A)24RCLR
Active-Low RAM Clear. The RCLR pin is used to clear (set to logic 1) all the
general-purpose RAM, but does not affect the RAM associated with the RTC. To
clear the RAM, RCLR must be forced to an input logic 0 during battery-backup
mode when VCC is not applied. The RCLR function is designed to be used
through a human interface (shorting to ground manually or by a switch) and not
to be driven with external buffers. This pin is internally pulled up. Do not use an
external pullup resistor on this pin.232726SQW
Square-Wave Output. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the
SQW pin can be changed by programming Register A, as shown in Table 1.
The SQW signal can be turned on and off using the SQWE bit in Register B. The
SQW signal is not available when VCC is less than VPF.242828VCC
DC Power Pin for Primary Power Supply. When VCC is applied within normal
limits, the device is fully accessible and data can be written and read. When
VCC is below VPF reads and writes are inhibited.
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
Detailed Description

The DS12885 family of RTCs provide 14 bytes of real-
time clock/calendar, alarm, and control/status registers
and 114 bytes (113 bytes for DS12C887 and
DS12C887A) of nonvolatile, battery-backed static RAM.
A time-of-day alarm, three maskable interrupts with a
common interrupt output, and a programmable square-
wave output are available. The devices also operate in
either 24-hour or 12-hour format with an AM/PM indica-
tor. A precision temperature-compensated circuit moni-
tors the status of VCC. If a primary power-supply failure
is detected, the devices automatically switch to a back-
up supply. The backup supply input supports a primary
battery, such as lithium coin cell. The devices are
accessed through a multiplexed address/data bus that
supports Intel and Motorola modes.
Oscillator Circuit

The DS12885 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crys-
tal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. An enable
bit in the control register controls the oscillator.
Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout.
High ESR and excessive capacitive loads are the major
contributors to long startup times. A circuit using a
crystal with the recommended characteristics and
proper layout usually starts within one second.
An external 32.768kHz oscillator can also drive the
DS12885. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is left
unconnected.
COUNTDOWN
CHAINX2
CRYSTAL
CL1CL2RTC REGISTERS
DS12885
Figure 1. Oscillator Circuit Showing Internal Bias Network
PARAMETERSYMBOLMINTYPMAXUNITS

Nominal
FrequencyfO32.768kHz
Series
ResistanceESR50kΩ
Load
CapacitanceCL6pF
Table 1. Crystal Specifications*

*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocksfor
additional specifications.
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