DS12887 ,Real Time ClockFEATURES Drop-in replacement for IBM AT computerclock/calendar Pin-compatible with the MC146818B ..
DS12887 ,Real Time ClockDS12887Real-Time ClockPIN ASSIGNMENT (Top View)
DS12887 ,Real Time ClockPIN DESCRIPTION Multiplex bus for pin efficiencyAD0–AD7 – Multiplexed Address/Data Bus Interfaced ..
DS12887 ,Real Time Clockblock diagram in Figure 1 shows the pin connections with the major internal functions of theDS12887 ..
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DS12887A ,Real time clockFEATURES PIN ASSIGNMENT (Top View) Drop-in replacement for IBM AT computerclock/calendarMOT1 24 VC ..
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DS12887
Real Time Clock
FEATURESDrop-in replacement for IBM AT computer
clock/calendarPin-compatible with the MC146818B and
DS1287Totally nonvolatile with over 10 years of
operation in the absence of powerSelf-contained subsystem includes lithium,quartz, and support circuitryCounts seconds, minutes, hours, days, day of
the week, date, month, and year with leap-
year compensation valid up to 2100Binary or BCD representation of time,calendar, and alarm12-hour or 24-hour clock with AM and PM in
12-hour modeDaylight Savings Time optionSelectable between Motorola and Intel bustimingMultiplex bus for pin efficiencyInterfaced with software as 128 RAM
locations14 bytes of clock and control registers–114 bytes of general-purpose RAMProgrammable square-wave output signalBus-compatible interrupt signals (IRQ)Three interrupts are separately software-
maskable and testableTime-of-day alarm once/second toonce/dayPeriodic rates from 122ms to 500msEnd-of-clock update cycleUnderwriters Laboratory (UL) recognized
PIN ASSIGNMENT (Top View)
Package Dimension Informationhttp:///TechSupport/DallasPackInfo.htm
PIN DESCRIPTIONAD0–AD7 – Multiplexed Address/Data Bus
N.C. – No Connection
MOT – Bus Type Selection – Chip SelectAS – Address StrobeW – Read/Write Input
DS – Data Strobe
RESET – Reset Input
IRQ – Interrupt Request Output
SQW – Square-Wave Output
VCC – +5V Supply
GND – Ground
ORDERING INFORMATION
DS12887
Real-Time Clock
DS12887
TYPICAL OPERATING CIRCUIT
DESCRIPTIONThe DS12887 real-time clock (RTC) plus RAM is designed to be a direct replacement for the DS1287.
The DS12887 is identical in form, fit, and function to the DS1287, and has an additional 64 bytes ofgeneral-purpose RAM. Access to this additional RAM space is determined by the logic level presented on
AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write-
protection circuitry are contained within a 24-pin dual in-line package. As such, the DS12887 is a
complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile
time-of-day clock, an alarm, a 100-year calendar, programmable interrupt, square-wave generator, and114 bytes of NV SRAM. The RTC is unique in that time-of-day and memory are maintained even in the
absence of power.
OPERATIONThe block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS12887. The following paragraphs describe the function of each pin.
DS12887
Figure 1. BLOCK DIAGRAM
POWER-UP/DOWN CONSIDERATIONSThe RTC function continues to operate, and all of the RAM, time, calendar, and alarm memory locationsremain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS12887 and
reaches a level of greater than 4.25V, the device becomes accessible after 200ms, provided that the
oscillator is running and the oscillator countdown chain is not in reset (Register A). This time period
allows the system to stabilize after power is applied. When VCC falls below 4.25V, the chip-select input is
internally forced to an inactive level regardless of the value of CS at the input pin. The DS12887 is,
therefore, write-protected. When the DS12887 is in a write-protected state, all inputs are ignored and alloutputs are in a high-impedance state. When VCC falls below a level of approximately 3V, the external
VCC supply is switched off, and an internal lithium energy source supplies power to the RTC and the
RAM memory.
DS12887
SIGNAL DESCRIPTIONS
GND, VCC – DC power is provided to the device on these pins. VCC is the +5V input. When 5V areapplied within normal limits, the device is fully accessible and data can be written and read. When VCC is
below 4.25V typical, reads and writes are inhibited. However, the timekeeping function continues
unaffected by the lower input voltage. As VCC falls below 3V typical, the RAM and timekeeper are
switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of �1
minute per month at +25�C, regardless of the voltage input on the VCC pin.
MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel
bus timing is selected. The pin has an internal pulldown resistance of approximately 20k�.
SQW (Square-Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by programming
Register A, as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in
Register B. The SQW signal is not available when VCC is less than 4.25V, typically.
Table 1. PERIODIC INTERRUPT RATE AND SQUARE-WAVE OUTPUT
FREQUENCY
AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins becauseaddress information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the secondportion of the cycle. Address/data multiplexing does not slow the access time of the DS12887 since the
bus change from address to data occurs during the internal RAM access time. Addresses must be valid
prior to the falling edge of AS/ ALE, at which time the DS12887 latches the address from AD0 to AD6.
DS12887
cycle is terminated and the bus returns to a high-impedance state as DS transitions low in the case of
Motorola timing or as RD transitions high in the case of Intel timing.
AS (Address Strobe Input) – A positive-going address-strobe pulse serves to demultiplex the bus. Thefalling edge of AS/ALE causes the address to be latched within the DS12887. The next rising edge that
occurs on the AS bus clears the address regardless of whether CS is asserted. Access commands should
be sent in pairs.
DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the level
of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode,DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read
cycles, DS signifies the time that the DS12887 is to drive the bidirectional bus. In write cycles the trailing
edge of DS causes the DS12887 to latch the written data. When the MOT pin is connected to GND, Intel
bus timing is selected. In this mode the DS pin is called Read (RD).RD identifies the time period when
the DS12887 drives the bus with read data. The RD signal is the same definition as the output-enableOE) signal on a typical memory.
W (Read/Write Input) – The R/W pin also has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level that indicates whether the current cycle is a read
or write. A read cycle is indicated with a high level on R/W while DS is high. A write cycle is indicated
when R/W is low during DS.
When the MOT pin is connected to GND for Intel timing, the R/W signal is an active-low signal called
WR. In this mode, the R/W pin has the same meaning as the write-enable signal (WE) on generic RAMs.
(Chip-Select Input) – The chip select signal must be asserted low for a bus cycle in the DS12887 tobe accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD
and WR for Intel timing. Bus cycles that take place without asserting CS latch addresses but no access
occur. When VCC is below 4.25V, the DS12887 internally inhibits access cycles by internally disabling
the CS input. This action protects both the RTC data and RAM data during power outages.
IRQ (Interrupt Request Output) – The IRQ pin is an active-low output of the DS12887 that can be
used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin, the processor
program normally reads the C register. The RESET pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an
external pullup resistor.
RESET (Reset Input) – The RESET pin has no affect on the clock, calendar, or RAM. On power-up, the
RESET pin can be held low for a time to allow the power supply to stabilize. The amount of time that
RESET is held low is dependent on the application. However, if RESET is used on power-up, the time
DS12887
RESET is low should exceed 200ms to ensure that the internal timer that controls the DS12887 on power-
up has timed out. When RESET is low and VCC is above 4.25V, the following occurs:
A) Periodic Interrupt Enable (PEI) bit is cleared to 0.
B) Alarm Interrupt Enable (AIE) bit is cleared to 0.
C) Update Ended Interrupt Flag (UF) bit is cleared to 0.
D) Interrupt Request Status Flag (IRQF) bit is cleared to 0.E) Periodic Interrupt Flag (PF) bit is cleared to 0.
F) The device is not accessible until RESET is returned high.
G) Alarm Interrupt Flag (AF) bit is cleared to 0.
H) H.IRQ pin is in the high impedance state.
I) Square-Wave Output Enable (SQWE) bit is cleared to 0.
J) Update Ended Interrupt Enable (UIE) is cleared to 0.
In a typical application RESET can be connected to VCC. This connection allows the DS12887 to go inand out of power fail without affecting any of the control registers.
ADDRESS MAPThe address map of the DS12887 is shown in Figure 2. The address map consists of 114 bytes of user
RAM; 10 bytes of RAM that contain the RTC time, calendar, and alarm data; and 4 bytes that are used for
control and status. All 128 bytes can be directly written or read except for the following:
1) Registers C and D are read-only.
2) Bit 7 of Register A is read-only.
3) The high-order bit of the seconds byte is read-only.
The contents of four registers (A, B, C, and D) are described in the Registers section.
Figure 2. ADDRESS MAP
DS12887
TIME, CALENDAR, AND ALARM LOCATIONSThe time and calendar information is obtained by reading the appropriate memory bytes. The time,
calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10
time, calendar, and alarm bytes can be either binary or binary coded decimal (BCD) format. Beforewriting the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a
logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10
time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of
Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be cleared after the data mode bit has been written toallow the RTC to update the time and calendar bytes. Once initialized, the RTC makes all updates in the
selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. Table 2 shows
the binary and BCD formats of the 10 time, calendar, and alarm locations. The 24–12 bit cannot be
changed without reinitializing the hour locations. When the 12-hour format is selected, the high-order bit
of the hours byte represents PM when it is a logic 1. The time, calendar, and alarm bytes are alwaysaccessible because they are double buffered. The 10 bytes are advanced once per second by 1 second and
checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem
exists where seconds, minutes, hours, etc., might not correlate. The probability of reading incorrect time
and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are
covered later in this text.
The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate
hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day
if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of
the three alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two mostsignificant bits of each byte set the “don’t care” condition when at logic 1. An alarm is generated each
hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute
with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm
bytes create an interrupt every second.
Table 2. TIME, CALENDAR, AND ALARM DATA MODES
DS12887
NV RAMThe 114 general-purpose NV RAM bytes are not dedicated to any special function within the DS12887.
They can be used by the processor program as nonvolatile memory and are fully available during the
update cycle.
INTERRUPTSThe RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500ms to 122�s. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when
the event occurs. A 0 in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately set
at an active level, although the interrupt initiating the event may have occurred much earlier. As a result,
there are cases where the program should clear such earlier initiated interrupts before first enabling new
interrupts.
When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set
independently of the state of the corresponding enable bit in Register B. The flag bit can be used in a
polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit that
software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using the
flag bits as they are cleared each time Register C is read. Double latching is included with Register C so
that set bits remain stable throughout the read cycle. All bits that are set (high) are cleared when read and
new interrupts that are pending during the read cycle are held until after the cycle is completed. One, two,
or three bits can be set when reading Register C. Each used flag bit should be examined when read to
ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt-enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a 1 whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic 1 in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS12887. The act of reading Register C clears all active flag bits and the IRQF
bit.
DS12887
OSCILLATOR CONTROL BITSWhen the DS12887 is shipped from the factory, the internal oscillator is turned off. This feature prevents
the lithium energy cell from being used until it is installed in a system. A pattern of 010 in bits 4 throughof Register A turns the oscillator on and enables the countdown chain. A pattern of 11X turns the
oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4
through 6 keep the oscillator off.
SQUARE-WAVE OUTPUT SELECTIONThirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of
Figure 1. The first purpose of selecting a divider tap is to generate a square-wave output signal on the
SQW pin. The RS0–RS3 bits in Register A establish the square-wave output frequency. These
frequencies are listed in Table 1. The SQW frequency selection shares its 1–of–15 selector with the
periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on
and off under program control with the square-wave enable bit (SQWE).
PERIODIC INTERRUPT SELECTIONThe periodic interrupt causes theIRQ pin to go to an active state from once every 500ms to once every
122�s. This function is separate from the alarm interrupt, which can be output from once per second to
once per day. The periodic interrupt rate is selected using the same Register A bits, which select the
square-wave frequency (Table 1). Changing the Register A bits affect both the square-wave frequency
and the periodic-interrupt output. However, each function has a separate enable bit in Register B. The
SQWE bit controls the square-wave output. Similarly, the periodic interrupt is enabled by the PIE bit in
Register B. The periodic interrupt can be used with software counters to measure inputs, create output
intervals, or await the next needed software function.
UPDATE CYCLEThe DS12887 executes an update cycle once per second regardless of the SET bit in Register B. When
the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, and alarm bytes
is frozen and will not update as the time increments. However, the time countdown chain continues to
update the internal copy of the buffer. This feature allows time to maintain accuracy independent of
reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar
information is consistent. The update cycle also compares each alarm byte with the corresponding time
byte and issues an alarm if a match or if a “don’t care” code is present in all three positions.
There are three methods that can handle access of the RTC that avoid any possibility of accessing
inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an
interrupt occurs after every update cycle that indicates that over 999ms are available to read valid time
and date information. If this interrupt is used, the IRQF bit in Register C should be cleared before leaving
the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
DS12887
changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to
read valid time/calendar data to exceed 244�s.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (Figure 3). Periodic interrupts that
occur at a rate of greater than tBUC allow valid time and date information to be reached at each occurrence
of the periodic interrupt. The reads should be complete within one (tPI/2 + tBUC) to ensure that data is not
read during the update cycle.
Figure 3. UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP
