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DS1265W-100
3.3V 8Mb Nonvolatile SRAM
FEATURES10 years minimum data retention in the
absence of external powerData is automatically protected during power
lossUnlimited write cyclesLow-power CMOS operationRead and write access times as fast as 100nsLithium energy source is electrically
disconnected to retain freshness until power is
applied for the first timeOptional industrial (IND) temperature range
of -40�C to +85�C
PIN ASSIGNMENT
PIN DESCRIPTIONA0–A19 - Address Inputs
DQ0–DQ7- Data In/Data Out- Chip Enable- Write Enable- Output Enable
VCC - Power (+3.3V)
GND - GroundNC- No Connect
DESCRIPTIONThe DS1265W 8Mb nonvolatile (NV) SRAMs are 8,388,608-bit, fully static, NV SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles that can be executed and noadditional support circuitry is required for microprocessor interfacing.
DS1265W
3.3V 8Mb Nonvolatile SRAM36-Pin Encapsulated Package
740mil Extended
A18
A14
VCC
DQ7
A16
A12
DQ0
DQ1
DQ6
DQ5GND
DQ2
DQ3
DQ4
DS1265W
READ MODEThe DS1265 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 20 address inputs(A0–A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either
tCO for CE or tOE for OE rather than tACC.
WRITE MODEThe DS1265 devices execute a write cycle whenever WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active), then WE
will disable the outputs in tODW from its falling edge.
DATA-RETENTION MODEThe DS1265W provides full functional capability for VCC greater than 3.0V and write protects by 2.8V.Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls
below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to
retain data. During power-up, when VCC rises above approximately 2.5V, the power-switching circuitconnects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 3.0V.
FRESHNESS SEALEach DS1265 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithiumenergy source is enabled for battery backup operation.
DS1265W
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +4.6V
Operating Temperature Range0°C to +70°C (-40°C to +85°C for IND parts)
Storage Temperature Range-40°C to +70°C (-40°C to +85°C for IND parts)
Soldering Temperature +260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 3.3V ��0.3V)
CAPACITANCE (TA = +25�C)
DS1265W
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC = 3.3V ��0.3V)
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
DS1265W
TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1265W
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
(TA = 25�C)
WARNING:Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE or WE. tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the outputbuffers remain in a high-impedance state during this period.
