DS1259S ,Battery Manager ChipPIN DESCRIPTION2 15VBAT VCCINC - No Connect3 14 NCBFV - Battery Input ConnectionBAT4 13 VCCONCBF - ..
DS125MB203SQE/NOPB ,12.5Gbps Dual Port MUX and Fanout Buffer 54-WQFN -40 to 85Block Diagram(1)Device InformationMB203PART NUMBER PACKAGE BODY SIZE (NOM)S_INA+S_INA-DS125MB203 WQ ..
DS1260-100 ,Smart BatteryPIN DESCRIPTION Low profile permits mounting on 0.5-inchPins 1, 2, 4, 7, 9, 10 and 14 are No-Conne ..
DS1260-25 ,Smart BatteryFEATURES PIN ASSIGNMENT Encapsulated lithium energy cell with shelflife beyond 10 years Available ..
DS1265AB-70 ,8M Nonvolatile SRAMFEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 36 V CCabsence of externa ..
DS1265W-100 ,3.3V 8Mb Nonvolatile SRAMPIN DESCRIPTIONA0–A19 - Address InputsDQ0–DQ7 - Data In/Data OutCE - Chip EnableWE - Write EnableOE ..
DTC114EKA T146 , NPN 100mA 50V Digital Transistors
DTC114EKA T146 , NPN 100mA 50V Digital Transistors
DTC114EKAT146 , NPN 100mA 50V Digital Transistors
DTC114EKAT146 , NPN 100mA 50V Digital Transistors
DTC114EKA-T146 , NPN 100mA 50V Digital Transistors
DTC114EM , NPN 100mA 50V Digital Transistors (Bias Resistor Built-in Transistors)
DS1259S
Battery Manager Chip
FEATURESFacilitates uninterruptible powerUses battery only when primary VCC is not
availableLow forward voltage dropPower fail signal interrupts processor or write
protects memoryConsumes less than 100 nA of battery currentLow battery warning signalBattery can be electrically disconnected upon
commandBattery will automatically reconnect when
VCC is appliedMates directly with DS1212 NonvolatileController x 16 Chip to back up 16 RAMsOptional 16-pin SOIC surface-mount package
PIN DESCRIPTION- No Connect
VBAT- Battery Input Connection- Battery Fail
Output Signal
BAT- Battery Output
RST- Reset InputGND- Ground- Power Fail
Output Signal
VCCO - RAM SupplyVCCI - +5V Supply
PIN ASSIGNMENT
DESCRIPTIONThe DS1259 Battery Manager Chip is a low-cost battery management system for portable and nonvolatile
electronic equipment. A battery connected to the battery input pin supplies power to CMOS electronic
circuits when primary power is lost through an efficient switch via the VCCO pins. When power is supplied
from the battery, the power-fail signal is active to warn electronic reset circuits of the power status.Energy loss during shipping and handling is avoided by pulsing reset, thereby causing the battery to be
isolated from other elements in the circuits.
DS1259
Battery Manager ChipVBAT
BAT
RST
GND
GND
VCCI
VCCI
VCCO
VCCO
16-Pin DIP Package (300-mil)
See Mech. Drawings Section
VBAT
BAT
RST
GND
GND
VCCI
VCCI
VCCO
VCCO
16-Pin SOIC Package (300-mil)See Mech. Drawings Section
DS1259
OPERATIONDuring normal operation, VCCI (Pins 15 and 16) is the primary energy source and power is supplied to
VCCO (Pins 12 and 13) through an internal switch at a voltage level of VCCI-0.2 volts at 250 mA. During
this time the power-fail signal (PF) is held high, indicating valid VCCI voltage (see Figure 1). However, if
the VCCI falls below the trip point (VTP), a level of 1.26 times the battery level (VBAT), the power-failsignal is driven low. As VCCI falls below the battery level, power is switched from VCCI to VBAT and the
battery supplies power to the uninterruptible output (VCCO) at VBAT-0.2 volts at 15 mA.
On power-up, as the VCCI supply rises above the battery, the primary energy source, VCCI, becomes the
supply. As VCCI rises above the trip point (VTP), the power fail signal is driven back to the high level.During normal operation, BAT (Pin 5) stays at the battery level regardless of the level of VCCI.
BATTERY FAILWhen power is being supplied from the primary energy source, BF (Pin 3) is held at a high level,
provided that the attached battery (VBAT) is greater than 2 volts. If the battery level should decrease to
below 2 volts, the BF signal is driven low, indicating a low battery. The BF signal is always low when
the PF signal is low.
RESETThe reset input can be used to prevent the battery from supplying power to VCCO and BAT even if VCCIfalls below the level of the battery. This feature is activated by applying a pulsed input on RST to high
level for 50ns minimum while primary power is valid (see Figure 2). When primary power is removed
after pulsing RST, the VCCO output and BAT will go to high impedance. The next time primary power is
applied such that VCCI is greater than VBAT, normal operation resumes and VCCO will be supplied by the
battery or VCCI. The BAT output will also return to the level of the battery. Figure 3 shows the DS1259 ina typical application.
BLOCK DIAGRAM Figure 1
DS1259
RESET TIMING Figure 2
TYPICAL APPLICATION Figure 3
DS1259
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-0.3V to +7.0V
Operating Temperature0°C to 70°C
Storage Temperature-55°C to +125°C
Soldering Temperature260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(0°C to 70°C)
DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 4.5 to 5.5V)
CAPACITANCE(TA = 25°C)
AC ELECTRICAL CHARACTERISTICS(0°C to 70°C; VCC = 4.0 to 5.5V)
DS1259
POWER-DOWN/POWER-UP CONDITION
NOTES:1. All voltages are referenced to ground.
2. Load capacity is 50 pF.
3. Measured with Pins 11, 12, 13, and 3 open.
4. VTP is the point that PF is driven low.
5. ICCO2 may be limited by the capability of the battery.
6. Trip point voltage for power-fail detect:
VTP = 1.26 x VBAT ± 250 mV
For 5% operation: VBAT = 3.7V max.
For 10% operation: VBAT = 3.5V max.
7. VBATF is the point that BF is driven low. These limits are for 0°C to 70°C operation.
8. Battery leakage is the internal energy consumed by the DS1259.
9. VCC = +5 volts, tA = 25°C.
:
www.ic-phoenix.com
.
