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DP84902MNSN/a5667avai1,7 Encoder/Decoder Circuit


DP84902M ,1,7 Encoder/Decoder CircuitFeaturesController Products with a 2-bit NRZ interface (such as Na-YOperates at 2-bit Non-Return to ..
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DP84902M
1,7 Encoder/Decoder Circuit
TL/F/11963
DP84902
1,7
Encoder/Decoder
Circuit
June 1994
DP84902
1,7 Encoder/Decoder Circuit
General Description
The DP84902is designedto performthe encodingandde-
codingfordisk memory systems.Itis designedto interface
directly with Integrated Read Channel Products (suchas
National Semiconductor’s DP84910) and with Disk Data
Controller Products witha 2-bit NRZ interface (suchasNa-
tional Semiconductor’s Advanced Disk Controllers). This
Encoder/Decoder (ENDEC) circuit employsa2/3 (1,7)Run
Length Limited (RLL) code typeand supportsthe hard sec-
tored format.
The DP84902hasthe optionof selecting either TTLor ECL
compatible code outputto interface with preamplifiers com-
monly usedin high datarate applications. Thisis accomm-
plishedbythe settingofabitinthe control register.
The ENDEC also includes write data precompensation con-
trol circuitry which detectsthe needfor write precompensa-
tion. This circuitry issues earlyandlate output signals nec-
essaryfor precompensation.The precompensation informa-
tionis generated againsta2T pattern. The precompensa-
tion circuitrycanbe bypassedbythe settingofabitinthe
control register. control reigsteris includedto configurethe ENDEC andto
select device operation options suchas output code inver-
sion, differential codeoutput, bypassingofthe encoder,and
theuseofan internal write clock.
The DP84902is availablein 20-pinSO and 20-pin SSO
packages.
Features Operatesat 2-bit Non-Returnto Zero (NRZ) Data Ratesto50 Mbits/second Single a5V Power Supply Operation Low Power Dissipation when TTL compatible code out-
putis selected. 150mWat50 Mbits/second NRZ Rate TTL Compatible Inputsand Outputs ECL Compatible Code Outputs (patented)are control
register selectable Two-bit NRZ Interface Supports Write Data Precompensation with Early and
Late output signals Selectable useof eitheran Internalor External Write
Clock Power Down Mode Included DC-Erasureis availableto support Analog Flaw Map-
ping Testing Bypass Mode available which permits Un-Encoded Test
Patternstobe issuedatthe CODEOUTPin
Block Diagram
TL/F/11963–1
FIGURE1. DP84902ENDEC Block Diagram
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
IBMÉ isaregistered trademarkof InternationalBusiness Machines Corporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
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