DP8421AVX-25 ,microCMOS Programmable 1M Dynamic RAM Controller/Driver(s) [Life-time buy]DP8420A/21A/22AmicroCMOSProgrammable256k/1M/4MDynamicRAMController/DriversJuly1992DP8420A/21A/22Ami ..
DP8422ATV-25 ,microCMOS Programmable 4M Dynamic RAM Controller/Driver(s)FeaturesYOn chip high precision delay line to guarantee criticalTheDP8420A/21A/22AdynamicRAMcontrol ..
DP8422AV-20 ,microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/DriversFeaturesYOn chip high precision delay line to guarantee criticalTheDP8420A/21A/22AdynamicRAMcontrol ..
DP8422AV-25 ,microCMOS Programmable 4M Dynamic RAM Controller/Driver(s) [Life-time buy]Features4.5.1 Address Latches and Column Increment11.0 ABSOLUTE MAXIMUM RATINGS4.5.2 Address Pipeli ..
DP8422V-33 ,microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/DriversFeaturesYOn chip high precision delay line to guarantee criticalThe DP8420V/21V/22V-33, DP84T22-25 ..
DP8422VX-33 ,microCMOS Programmable 256K/1M/4M Dynamic RAM Controller/Drivers [Life-time buy]FeaturesYOn chip high precision delay line to guarantee criticalThe DP8420V/21V/22V-33, DP84T22-25 ..
DS90CF364MTDX ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn 20 to 65 MHz shift clock supportThe DS90C363 transmitter converts 21 bits of CMOS/TTLdata ..
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DS90CF366MTD ,+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85 MHzGeneral Descriptionproblems associated with wide, high speed TTL interfaces.The DS90CF386 receiver ..
DS90CF383AMTD ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz [Life-time buy]Featuresn 20 to 65 MHz shift clock supportThe DS90C383A/DS90CF383A transmitter converts 28 bitsof C ..
DS90CF383AMTDX ,+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz [Life-time buy]Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
DS90CF383BMT ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHzBlock DiagramDS90C383B20098401Order Number DS90C383BMTSee NS Package Number MTD56®TRI-STATE is a re ..
DP8421AV-20-DP8421AV-25-DP8421AVX-25-DP8422AV-25
microCMOS Programmable 1M Dynamic RAM Controller/Driver(s) [Life-time buy]
TL/F/8588
DP8420A/21A/22A
microCMOS
Programmable
256k/1M/4M
Dynamic
RAM
Controller/Drivers
July 1992
DP8420A/21A/22A microCMOS Programmable
256k/1M/4M Dynamic RAM Controller/Drivers
General Description
The DP8420A/21A/22Adynamic RAMcontrollers providea
low cost, single chip interface between dynamic RAMand
all8-,16-and 32-bit systems.The DP8420A/21A/22A gen-
erateall the required access control signal timingfor
DRAMs.An on-chip refresh request clockis usedto auto-
matically refreshthe DRAM array. Refreshesand accesses
are arbitratedon chip.If necessary,a WAITor DTACKout-
put inserts wait statesinto system access cycles, including
burst mode accesses. RASlow time during refreshesand
RAS precharge time after refreshesand backto backac-
cessesare guaranteed throughthe insertionofwait states.
Separate on-chip precharge countersfor each RAS output
canbe usedfor memory interleavingto avoid delayed back back accesses becauseof precharge.An additionalfea-
tureofthe DP8422Ais two access portsto simplify dual
accessing. Arbitration among these ports and refreshis
doneon chip.
FeaturesOn chip high precision delaylineto guarantee critical
DRAM access timing parameters microCMOS processforlow power High capacitance driversfor RAS, CAS,WE and DRAM
addresson chipOn chip supportfor nibble, page and static column
DRAMs Byte enable signalson chip allow byte writingina word
sizeupto32bits withno external logic Selectionof controller speeds:20 MHzand25 MHzOn board Port A/PortB (DP8422A only)/refresh arbitra-
tion logic Direct interfacetoall major microprocessors (applica-
tion notes available)4 RASand4 CAS drivers(the RAS and CAS configura-
tionis programmable) ofPins Ýof Address Largest Direct Drive Access
Control (PLCC) Outputs DRAM Memory Ports
Possible Capacity Available
DP8420A 68 9 256kbit 4Mbytes Single AccessPort
DP8421A 68 10 1 Mbit 16Mbytes Single AccessPort
DP8422A 84 11 4 Mbit 64Mbytes Dual AccessPorts(A andB)
Block Diagram
DP8420A/21A/22A DRAM Controller
TL/F/8588–5
FIGURE1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
StaggeredRefreshTM isatrademark ofNationalSemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
