DM74LS574WM ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional DescriptionThe DM74LS574 consists of eight edge-triggered flip-flops sition. With the Ou ..
DM74LS670MX , 3-STATE 4-by-4 Register FileGeneral Descriptionwriting, and is limited in speed only by the write time (27 nsThese register fil ..
DM74LS670N ,3-STATE 4-by-4 Register FileFeatures
I Alternate Military/Aerospace device (54LS670) is avail-
able. Contact a National Sem ..
DM74LS670N ,3-STATE 4-by-4 Register FileGeneral Description
These register tiles are organized as 4 words of 4 bits each,
and separate ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DS2415 ,1-Wire Time ChipPIN DESCRIPTION Built-in multidrop controller ensurescompatibility with other MicroLAN products Pi ..
DS2415P ,1-Wire Time Chipfeaturescan be used to add functions such as calendar, time and date stamp and logbook to any type ..
DS2415P/T&R ,1-Wire Time ChipPIN DESCRIPTION Built-in multidrop controller ensurescompatibility with other MicroLAN products Pi ..
DS2415P-W ,1-Wire Time Chipfeaturescan be used to add functions such as calendar, time and date stamp, and logbook to any type ..
DS2423P ,4kbit 1-Wire RAM with CounterPIN DESCRIPTIONcompatibility with other MicroLAN productsPin 1 Ground Directly connects to a singl ..
DS2430 ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DM74LS574N-DM74LS574WM
Octal D-Type Flip-Flop with 3-STATE Outputs
DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs March 1988 Revised March 2000 DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The DM74LS574 is a high speed low power octal flip-flop with a buffered common Clock (CP) and a buffered com- mon Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identical to the DM74LS374 except for the pinouts. Ordering Code: Order Number Package Number Package Description DM74LS574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram V = Pin 20 CC GND = Pin 10 Truth Table Inputs Outputs Dn CP OE On HLH LLL XX H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = HIGH-to-LOW Clock (CP) transition © 2000 DS009815
