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DM74LS26MNSN/a1062avaiQuad 2-Input NAND Gate with High Voltage Open-Collector Outputs
DM74LS26NNSN/a105avaiQuad 2-Input NAND Gate with High Voltage Open-Collector Outputs


DM74LS26M ,Quad 2-Input NAND Gate with High Voltage Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
DM74LS26N ,Quad 2-Input NAND Gate with High Voltage Open-Collector OutputsDM74LS26 Quad 2-Input NAND Gate with High Voltage Open-Collector OutputsAugust 1986Revised March 20 ..
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DM74LS273WM ,8-Bit Register with ClearFunctional DescriptionThe DM74LS273 is an 8-bit parallel register with a commonClock and common Mas ..
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DM74LS26M-DM74LS26N
Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs
DM74LS26 Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs August 1986 Revised March 2000 DM74LS26 Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function. The open-collector out- puts require external pull-up resistors for proper logical operation. These gates feature high-voltage output ratings (up to 15V) for interfacing with 12V systems. Although the outputs are rated for 15V, the device supply is still rated for 5V. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM74LS26M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS26N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs Output AB Y LL H LH H HL H HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006358
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