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DM74AS373WMNSN/a1999avaiOctal D-Type Transparent Latch with 3-STATE Outputs
DM74AS373WMXNSN/a921avaiOctal D-Type Transparent Latch with 3-STATE Outputs
DM74AS373WMXFAIRCHILN/a1000avaiOctal D-Type Transparent Latch with 3-STATE Outputs


DM74AS373WM ,Octal D-Type Transparent Latch with 3-STATE OutputsDM74AS373 Octal D-Type Transparent Latch with 3-STATE OutputsApril 1984Revised March 2000DM74AS373O ..
DM74AS373WMX ,Octal D-Type Transparent Latch with 3-STATE OutputsFeaturesThese 8-bit registers feature totem-pole 3-STATE outputs ■ Switching specifications at 50 p ..
DM74AS373WMX ,Octal D-Type Transparent Latch with 3-STATE OutputsFeaturesThese 8-bit registers feature totem-pole 3-STATE outputs ■ Switching specifications at 50 p ..
DM74AS374N ,Octal D-Type-Edge-Triggered Flip-Flops With 3-STATE OutputsFeaturesThese 8-bit registers feature totem-pole 3-STATE outputs ■ Switching specifications at 50 p ..
DM74AS573N ,Octal D-Type Transparent Latch With 3-STATE OutputsFeaturesThese 8-bit registers feature totem-pole 3-STATE outputs ■ Switching specifications at 50 p ..
DM74AS573N ,Octal D-Type Transparent Latch With 3-STATE OutputsDM74AS573 Octal D-Type Transparent Latch with 3-STATE OutputsOctober 1986Revised March 2000DM74AS57 ..
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DS18S20 ,1-Wire Parasite-Power Digital ThermometerElectrical Characteristics(V = 3.0V to 5.5V, T = -55°C to +125°C, unless otherwise noted.)DD APARAM ..
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DM74AS373WM-DM74AS373WMX
Octal D-Type Transparent Latch with 3-STATE Outputs
DM74AS373 Octal D-Type Transparent Latch with 3-STATE Outputs April 1984 Revised March 2000 DM74AS373 Octal D-Type Transparent Latch with 3-STATE Outputs General Description Features These 8-bit registers feature totem-pole 3-STATE outputs � Switching specifications at 50 pF designed specifically for driving highly-capacitive or rela- � Switching specifications guaranteed over full tempera- tively low-impedance loads. The high-impedance state and ture and V range CC increased high-logic-level drive provide these registers with � Advanced oxide-isolated, ion-implanted Schottky TTL the capability of being connected directly to and driving the process bus lines in a bus-organized system without need for inter- � Functionally and pin for pin compatible with LS and ALS face or pull-up components. They are particularly attractive TTL counterparts for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. � Improved AC performance over LS and ALS TTL coun- terparts The eight latches of the DM74AS373 are transparent D- type latches, meaning that while the enable (G) is HIGH � 3-STATE buffer-type outputs drive bus lines directly the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number Package Description DM74AS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74AS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006309
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