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DM74AS161NNSCN/a25avaiSynchronous 4-Bit Binary Counter with Asynchronous Clear
DM74AS161NNSN/a42avaiSynchronous 4-Bit Binary Counter with Asynchronous Clear
DM74AS163MFAIRCHILN/a7avaiSynchronous 4-Bit Binary Counter with Asynchronous Clear
DM74AS163NN/a12avaiSynchronous 4-Bit Binary Counter with Asynchronous Clear


DM74AS161N ,Synchronous 4-Bit Binary Counter with Asynchronous ClearDM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter ..
DM74AS161N ,Synchronous 4-Bit Binary Counter with Asynchronous ClearDM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter ..
DM74AS163M ,Synchronous 4-Bit Binary Counter with Asynchronous ClearGeneral Descriptioncounters for n bit synchronous application without addi-These synchronous preset ..
DM74AS163N ,Synchronous 4-Bit Binary Counter with Asynchronous ClearGeneral Descriptioncounters for n bit synchronous application without addi-These synchronous preset ..
DM74AS169AMX ,Synchronous 4-Bit Binary Up/Down Counterapplications without additional gating.Both count enable inputs (P and T) must be LOW to count.The ..
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DM74AS161N-DM74AS163M-DM74AS163N
Synchronous 4-Bit Binary Counter with Asynchronous Clear
DM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter April 1984 Revised March 2000 DM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter The carry look ahead circuitry provides for cascading General Description counters for n bit synchronous application without addi- These synchronous presettable counters feature an inter- tional gating. Instrumental in accomplishing this function nal carry look ahead for application in high speed counting are two count-enable inputs (P and T) and a ripple carry designs. The DM74AS161 and DM74AS163 are 4-bit output. Both count-enable inputs must be HIGH to count. binary counters. The DM74AS161 clear asynchronously, The T input is fed forward to enable the ripple carry output. while the DM74AS163 clear synchronously. The carry out- The ripple carry output thus enabled will produce a high put is decoded to prevent spikes during normal counting level output pulse with a duration approximately equal to mode of operation. Synchronous operation is provided by the high level portion of QA output. This high level overflow having all flip-flops clocked simultaneously so that outputs ripple carry pulse can be used to enable successive cas- change coincident with each other when so instructed by caded stages. HIGH-to-LOW level transitions at the enable count enable inputs and internal gating. This mode of oper- P or T inputs of the DM74AS161 and DM74AS163, may ation eliminates the output counting spikes which are nor- occur regardless of the logic level on the clock. mally associated with asynchronous (ripple clock) The DM74AS161 and DM74AS163 feature a fully indepen- counters. A buffered clock input triggers the four flip-flops dent clock circuit. Changes made to control inputs (enable on the rising (positive-going) edge of the clock input wave- P or T, or load) that will modify the operating mode will form. have no effect until clocking occurs. The function of the These counters are fully programmable, that is, the outputs counter (whether enabled, disabled, loading or counting) may each be preset to either level. As presetting is syn- will be dictated solely by the conditions meeting the stable chronous, setting up a low level at the LOAD input disables set-up and hold times. the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of Features enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on � Switching specifications at 50 pF the clock or enable inputs. � Switching specifications guaranteed over full tempera- The DM74AS161 clear function is asynchronous. A low ture and V range CC level at the clear input sets all four of the flip-flop outputs � Advanced oxide-isolated, ion-implanted Schottky TTL LOW regardless of the levels of clock, load or enable process inputs. This counter is provided with a clear on power-up � Functionally and pin-for-pin compatible with Schottky feature. The DM74AS163 clear function is synchronous; and low power Schottky TTL counterpart and a low level at the clear input sets all four of the flip-flop � Improved AC performance over Schottky and low power outputs LOW after the next clock pulse, regardless of the Schottky counterparts levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maxi- � Synchronously programmable mum count desired can be accomplished with one external � Internal look ahead for fast counting NAND gate. The gate output is connected to the clear input � Carry output for n-bit cascading to synchronously clear the counter to all LOW outputs. � Synchronous counting LOW-to-HIGH transitions at the clear input of the DM74AS163 is also permissible regardless of the levels of � Load control line logic on the clock, enable or load inputs. � ESD inputs Ordering Code: Order Number Package Number Package Description DM74AS161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74AS163M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006291
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