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DG307AAK/883B |DG307AAK883BMAXIMN/a2498avaiCMOS Analog Switches


DG307AAK/883B ,CMOS Analog SwitchesFeatures . Monolithic Low Power CMOS . Latch-Up Proof Construction . Fully Compatible 2nd Sour ..
DG307ABK ,CMOS dual and quad analog switch.Features . Monolithic Low Power CMOS . Latch-Up Proof Construction . Fully Compatible 2nd Sour ..
DG307ACJ ,CMOS Analog SwitchsFeatures . Monolithic Low Power CMOS . Latch-Up Proof Construction . Fully Compatible 2nd Sour ..
DG307ACK ,CMOS Analog SwitchsGeneral Doccription Maxim's DG304-DG307 and DG304A-DG307A CMOS dual and quad analog switches co ..
DG307ACWE ,CMOS Analog SwitchsELECTRICAL CHARACTERISTICS (Continued) N' = +15V, V' = -15V, GND = 0V, TA = 25''C, unless otherwis ..
DG307AK ,CMOS Analog SwitchsFeatures . Monolithic Low Power CMOS . Latch-Up Proof Construction . Fully Compatible 2nd Sour ..
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DG307AAK/883B
CMOS Analog Switches
19-0310; Rev 1; 5/04
Gonoral Description
Maxim's DG304-DG307 and DG304A-DG307A CMOS
dual and quad analog switches combine low power
operation with fast switching times and superior DC
and AC switch characteristics. On resistance is less
than tion and is essentially constant over the analog
signal range. Device specifications are ideal for battery
powered circuitry.
These switches are available in a variety of formats as
outlined below in the Pin Configurations section. The
switch control logic inputs are compatible with CMOS
logic. Also featured are "break-before-make" switching
and low charge injection.
Maxim's DG304-DG307 and DG304A-DG307A families
are electrically compatible and pin compatible with
the original manufacturer's devices. All devices will
operate with power supplies ranging from :t5V to
118V. Single supgly operation is implemented by
connecting V‘ to ND.
Applications
Portable Instruments
Low Power Sample/Holds
Power Supply Switching
Programmable Gain Amplifiers
SPDT and DPDT Functions
Process Control and Telemetry
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CMOS Analog Switches
Features
. Monolithic Low Power CMOS
. Latch-Up Proof Construction
. Fully Compatible 2nd Source
. Low On Resistance, . Fast Switching Time
t g' to IC Analog Signal Range
. Single Supply Capability
Ordering Information
PART TEMP. RANGE PACKAGE
DG304C/D iPC to +70°C Dice
DG304C0 tPC to +70°C 14 Lead Plastic DIP
DGSMCWE tPC to +70''C 16 Lead Wide so
DG304CK (PC to +70°c 14 Lead CEHDIP
DGSMBWE -25''C to +85°C 16 Lead Wide so
DG3048K AW'C to +85°C 14 Lead CERDIP
DGSMBA -25''C to +85°C 10 Lead Metal Can
DG304AK -55''C to +12tPC 14 Lead CERDIP
DG304AA -55°C to +125°C 10 Lead Metal Can
Ordering Information continued at end of data sheet.
Pin Configurations,
* Dual SPST DG304/DG304A
*SPDT DG305/DG305A
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LOGIC SWITCH t SWITCH 2
0 OFF ON
1 ON OFF
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SWITCH LOGIC 8mm
'Note: Pins 6 and 9 of the
OFF 16-lead Small Outline Package 0 OFF
are not connected.
Switch states are for Logic "I" Inputs (Positive Logic).
* Dual DPST DG306/DG306A
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0 OFF ON
1 ON OFF
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Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at .
http://www.
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CMOS Analog Switches
'"N ABSOLUTE MAXIMUM RATINGS
I Voltages Referenced to V' Operating Temperature (A Suffix) ....... -55°C to 125''C
si. V’ (DG304-DG307) ................................ 36V (B Suffix) . .. -25°C to 85°C
N l/' (DG304A-DG307A) ............................. 44V (C Suffix) .......... tPC to 70''C
GND m............................................. 25V Lead Temperature (Soldering 10 sec.) ........... +300°C
Ct Digital Inputs, vs, vD (Note 1) ....... MV to iv' + 4V) or Power Dissipation'
a 30mA, whichever occurs first. Cerdip (K) (Derate 11mW/°C above 75°C) ....... 825mW
Current, Any Terminal Except S or D ............. 30mA Plastic DIP (J) (Derate 6.5mW/°C above 25''C) .. 470mW
Continuous Current, 8 or D ...................... 30mA Metal Can (A) (Derate 6rnW/''C above 75''C) .... 450mW
(Pulsed at 1msec. 10% duty cycle max) ........ 100mA
Storage Temperature (A & B Suffix) ..... -65''C to 15tPC ' Device mounted with all leads soldered or welded to PC
N (c Suffix) ......... -65°C to 125°C board. W -
a Stresses listed under ‘ubsoluro Maximum Ratings" may be applied (one at a time) to devices without resulting in permanent damage. These are
q stress ratings only, and functional operation of (he davicg at thes. or any or/yy conditions above those indicated in tre.opertyyt,!t.l sections of the
, specifications is not implied. Exposure to absolute manmum ratings conditions for extended periods may tttttstat dawco rtrtiabittty.
ttt ELECTRICAL CHARACTERISTICS (V' = +15V, V‘ = -15V, GND = 0V, TA = 25"C, unless otherwise indicated)
Ct DG3tM-DG307A DG304-DG30rB/C
DG3tMA-Dtt307AA DG304A-DG30rABm
a PARAMETER SYMBOL TEST CONDITIONS UNITS
MIN TYP MAX MIN TYP MAX
lil (Note 2) (Note 3) (Note 2) (Note 3)
N Analog Signal Range VANALOG Is = 10mA. VIn = 3.5V or 11.0V -15 15 -15 15 V
a tlryt-styce r Is = -10mA, VD = 10V 30 '50 30 50 n
A ON Resistance DS(on) IS = 10mA, vD = -10v 30 50 30 50
" 5 Source OFF I Vs = 14v. Vo = -14V 0.1 1 0.1 5
m L" Leakage Current Mott) Vin = 3.5V VS = -14V, VD = 14V -1 -0.1 -5 -O.1
Ct t Drain OFF v = 11.0V Vs = -14V. VI: = 14V 0.1 1 0.1 5
a bon In nA
Leakage Current vs = 14V, lh, = -14v -1 -0.1 -5 -0.1
lil Drain ON I VD = VS = 14V 01 1 0.1 5
'N' Leakage Current Dion) VD = Vs = -14V -2 Ah1 -5 -O.1
A Input Current/ I Vin = 5.0V -1 -0.001 -l Ah001
A ct, Voltage High INN Vin = 15V 0.001 1 0.001 1
V g I tC t/ PA
- npu urren = - -
q Voltage Low IINL Vin ov 1 -O.001 1 -0.001
Ct Turn-ON Time ton . . . . . 110 250 110 250
a . See Switching Time Test Circuit
Turn-OFF Time u 70 150 70 150
See Break-Before-Make
g 1t,t'irfore-Mak'' ton-to" Time Test Circuit 50 50
D6305(A)/DG307(A) Only
Charge Injection Q CL = 10nF, R99" = on, VPan = 0V 12 12 PC
Source OFF
‘0 . . CS Vs = 0V 14 14
i Capacitande (oft) f = 1MHz,
< Drain OFF V, = 3.5V -
F. Capacitance 09W” m or VD - W 14 14
ta V = 11.0V pF
ChanneI-ON Cm ) ' in = =
Capacitance 03(3) Vs VD ov 40 40
. Vin = 0V 6
Input Capacitance tk, f = 1MHz
vin = 15V 7 7
Off Isolation (Note 4) 62 62
C talk Vin = ov, RL = IKQ dB
ross V =1V ,f=500kHz
(Channel to Channel) s RMS 74 74
(Se Notes next page).
2 IVIIJXl/VI

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