| Partno |
Mfg |
Dc |
Qty |
Available | Descript |
| CY7C1550KV18-450BZC |
CY|Cypress |
N/a |
55 |
 |
72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C15631KV18-450BZC CY
CY7C1550KV18-450BZC , 72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C15632KV18-400BZXC ,72-Mbit QDR?II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)Block Diagram – CY7C15632KV1818D[17:0]Write Write Write Write20AddressAReg Reg Reg Reg(19:0)Registe ..
CY7C15632KV18-450BZC ,72-Mbit QDR?II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)Characteristics . 23Write Cycle Descriptions ..10 Switching Waveforms ....... 25IEEE 1149.1 Serial ..
CY7C15632KV18-450BZXC ,72-Mbit QDR?II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)Features Configurations Separate Independent Read and Write Data Ports With Read Cycle Latency of 2 ..
CY7C15632KV18-450BZXI ,72-Mbit QDR?II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)Characteristics . 21Valid Data Indicator (QVLD) ....7 Capacitance .....21PLL ......7 Thermal Resist ..
D5C031-50 , 300 gate CMOS pld
D5C031-50 , 300 gate CMOS pld
D5C032-30 , 8-MACROCELL CMOS PLD
