| Partno |
Mfg |
Dc |
Qty |
Available | Descript |
| CY7C12501KV18-400BZC |
CY|Cypress |
N/a |
1300 |
 |
36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C12501KV18-400BZXC CY
CY7C12501KV18-450BZXC CY
CY7C12501KV18-400BZC , 36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1250KV18-400BZC ,36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)Characteristics . 22Write Cycle Descriptions ....8 Switching Waveforms ....... 23Write Cycle Descri ..
CY7C1250KV18-400BZI ,36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)Block Diagram – CY7C1248KV18Write Write20AReg Reg(19:0)AddressRegister18LDKOutputCLK R/WLogicKGen.C ..
CY7C1250KV18-400BZXC ,36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)Functional Description900 MHz) at 450 MHz The CY7C1248KV18, and CY7C1250KV18 are 1.8 V Available in ..
CY7C1263KV18-400BZC ,36-Mbit QDR?II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2 ..
D38NH02L , N-channel 24V - 0.011ohm - 38A - DPAK/IPAK STripFET TM III Power MOSFET
D3FJ10 , Schottky Barrier Diode
D3FJ10 , Schottky Barrier Diode
