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CY62256VLL-70SNC 257pcs , SOP , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM
Partno Mfg Dc Qty Available
CY62256VLL-70SNC N/a 257
CY62256VLL-70SNC from CY, Cypress 546pcs , SOP-28 , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM
CY62256VLL-70SNC from CYPRESS  , Cypress 2pcs , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM
CY62256VLL-70SNC from CRY, 30pcs , SOP , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM
CY62256VLL-70SNC from CYP, Cypress 826pcs , SOP , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM
CY62256VLL-70SNC from CYPRESS, Cypress 100pcs , SMD , Alternate PN:CY62256VLL70SNC,256K (32K x 8) Static RAM

Characteristics Over the Operating Range CY62256V-70[2]Parameter Description Test Conditions Min. Typ. Max. UnitV Output HIGH Voltage I = −1.0 mA V = 2.7V 2.4 VOH OH CC V Output LOW Voltage I = 2.1 mA V = 2.7V 0.4 VOL OL CC V Input HIGH Voltage 2.2 V VIH CC+0.3VV Input Leakage Voltage –0.5 0.8 VILI Input Leakage Current GND < V < V Com’l, Ind’l –1 +1 µAIX IN CCAutomotive -10 +10 µAI Output Leakage Current GND < V < V , Output Disabled Com’l, Ind’l –1 +1 µAOZ IN CCAutomotive -10 +10 µAI V Operating Supply V = 3.6V, I = 0 mA, All ranges 11 30 mACC CC CC OUTCurrent f = f = 1/tMAX RCI Automatic CE Power-down V = 3.6V, CE > V , All ranges 100 300 µASB1 CC IHCurrent— TTL Inputs V > V or V < V , f = fIN IH IN IL MAXI Automatic CE Power-down V = 3.6V, CE > V – 0.3V Com’l 0.1 5SB2 CC CCCurrent— CMOS Inputs V > V – 0.3V or V < 0.3V, f = 0IN CC INInd’l 10Automotive 130Electrical featuresthrough A ). Reading the device is accomplished by selecting14• TTL-compatible inputs and outputsthe device and enabling the outputs, CE and OE active LOW,• Automatic power-down when deselectedwhile WE remains inactive or HIGH. Under these conditions,• CMOS for optimum speed/power the contents of the location addressed by the information onaddress pins are present on the eight data input/output pins.• Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, and The input/output pins remain in a high-impedance state unlessreverse 28-lead TSOP-1 packagethe chip is selected, outputs are enabled, and write enable(WE) is HIGH. Logic featuresthrough A ). Reading the device is accomplished by selecting14• TTL-compatible inputs and outputsthe device and enabling the outputs, CE and OE active LOW,• Automatic power-down when deselectedwhile WE remains inactive or HIGH. Under these conditions,• CMOS for optimum speed/power the contents of the location addressed by the information onaddress pins are present on the eight data input/output pins.• Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, and The input/output pins remain in a high-impedance state unlessreverse 28-lead TSOP-1 packagethe chip is selected, outputs are enabled, and write enable(WE) is HIGH. Logic Block DiagramI/O0INPUTBUFFERI/O1A10A9I/O2A8A7I/OA36512 × 512A5ARRAYA I/O4 4A3A2I/O5CEI/O6POWERWE COLUMNDOWNDECODERI/O7OENote:1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.Cypress Semiconductor Corporation • 3901NorthFirstStreet • SanJose • • Document #: 38-05057 Rev. *D Revised June 28, 2004ROW DECODERA14A13A12A11A1A0SENSE AMPS CY62256VProduct PortfolioPower DissipationV Range (V) Speed Operating, I (mA) Standby, I (µA)CC CC SB2[2] [2] [2]Product Range Min. Typ. Max. (ns) Typ. Max. Typ. Max.CY62256VLL Com’l / Ind’l 2.7 3.0 3.6 70 11 30 0.1 5 CY62256VLL Automotive 2.7 3.0 3.6 70 11 30 0.1 130CY62256V25LLCom’l 2.3 2.5 2.7 100 9 15 0.1 4 Pin Configurations Narrow SOICTop ViewA 28 V15 CCA 27 WE26A8 A11 7 2112 OE 22 A0A 2637 A4 A 96 A 2010 13 A1 23 CEA 4 A258 3 10 AA 5 1914 A I/O9 24 7224A A 11 I/OA 4 18 I/O9 5 8 02 A 25 633 12 I/O 17 I/OA 23 A7 1 A 26A 510 6 41TSOP I13 162 I/O I/OA 27 TSOP I6 2 WE 422A OE11 7Reverse Pinout 14 15 I/OA 1 GND 3V 28 Top View5CC21 AA8 0 28 15 I/O 14 GND12 V Top View A 13CC 5(not to scale)16 13I/O20 27 I/O A 2 2A CE 69 WE (not to scale) 41317 12A 26 I/O A7 3 I/O14 5A 191014 I/O18 117 I/OA 25 A 43 I/O 8 061811 I/O 10 AI/O 24 196 A I/O A 5 1402 7 9920 A17 23 A12 I/O A CE 6 13I/O 105 11822 21 A A 7 A12OE 0 11I/O13 16 I/O24I/OGND 1514 3Pin DefinitionsPin Number Type Description1-10, 21, 23-26 Input A -A . Address Inputs0 1411-13, 15-19 Input/Output I/O -I/O . Data lines. Used as input or output lines depending on operation0 727 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READis conducted20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pinsbehave as outputs. When deasserted HIGH, I/O pins are three-stated, and act asinput data pins14 Ground GND. Ground for the device28 Power Supply Vcc. Power supply for the deviceNotes:2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V Typ., T = 25°C, and t = 70 ns.CC CC A AA Document #: 38-05057 Rev. *D Page 2 of 13 CY62256VStatic Discharge Voltage...... > 2001VMaximum Ratings(per MIL-STD-883, Method 3015)(Above which the useful life may be impaired. For user guide-Latch-up Current....... > 200 mAlines, not tested.)Operating RangeStorage Temperature ......–65°C to +150°CAmbient Ambient Temperature withTemperature Power Applied–55°C to +125°C[4]Device Range (T ) VA CCSupply Voltage to Ground PotentialCY62256V Commercial 0°C to +70°C 2.7V to (Pin 28 to Pin 14) ....... –0.5V to +4.6V3.6VIndustrial −40°C to DC Voltage Applied to Outputs+85°C [3]in High-Z State –0.5V to V + 0.5VCCAutomotive −40°C to [3]DC Input Voltage ......–0.5V to V + 0.5VCC+125°C Output Current into Outputs (LOW) ..20 mACY62256V25 Commercial 0°C to +70°C 2.3V to 2.7VElectrical featuresthrough A ). Reading the device is accomplished by selecting14• TTL-compatible inputs and outputsthe device and enabling the outputs, CE and OE active LOW,• Automatic power-down when deselectedwhile WE remains inactive or HIGH. Under these conditions,• CMOS for optimum speed/power the contents of the location addressed by the information onaddress pins are present on the eight data input/output pins.• Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, and The input/output pins remain in a high-impedance state unlessreverse 28-lead TSOP-1 packagethe chip is selected, outputs are enabled, and write enable(WE) is HIGH. Logic Block DiagramI/O0INPUTBUFFERI/O1A10A9I/O2A8A7I/OA36512 × 512A5ARRAYA I/O4 4A3A2I/O5CEI/O6POWERWE COLUMNDOWNDECODERI/O7OENote:1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.Cypress Semiconductor Corporation • 3901NorthFirstStreet • SanJose • • Document #: 38-05057 Rev. *D Revised June 28, 2004ROW DECODERA14A13A12A11A1A0SENSE AMPS CY62256VProduct PortfolioPower DissipationV Range (V) Speed Operating, I (mA) Standby, I (µA)CC CC SB2[2] [2] [2]Product Range Min. Typ. Max. (ns) Typ. Max. Typ. Max.CY62256VLL Com’l / Ind’l 2.7 3.0 3.6 70 11 30 0.1 5 CY62256VLL Automotive 2.7 3.0 3.6 70 11 30 0.1 130CY62256V25LLCom’l 2.3 2.5 2.7 100 9 15 0.1 4 Pin Configurations Narrow SOICTop ViewA 28 V15 CCA 27 WE26A8 A11 7 2112 OE 22 A0A 2637 A4 A 96 A 2010 13 A1 23 CEA 4 A258 3 10 AA 5 1914 A I/O9 24 7224A A 11 I/OA 4 18 I/O9 5 8 02 A 25 633 12 I/O 17 I/OA 23 A7 1 A 26A 510 6 41TSOP I13 162 I/O I/OA 27 TSOP I6 2 WE 422A OE11 7Reverse Pinout 14 15 I/OA 1 GND 3V 28 Top View5CC21 AA8 0 28 15 I/O 14 GND12 V Top View A 13CC 5(not to scale)16 13I/O20 27 I/O A 2 2A CE 69 WE (not to scale) 41317 12A 26 I/O A7 3 I/O14 5A 191014 I/O18 117 I/OA 25 A 43 I/O 8 061811 I/O 10 AI/O 24 196 A I/O A 5 1402 7 9920 A17 23 A12 I/O A CE 6 13I/O 105 11822 21 A A 7 A12OE 0 11I/O13 16 I/O24I/OGND 1514 3Pin DefinitionsPin Number Type Description1-10, 21, 23-26 Input A -A . Address Inputs0 1411-13, 15-19 Input/Output I/O -I/O . Data lines. Used as input or output lines depending on operation0 727 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READis conducted20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pinsbehave as outputs. When deasserted HIGH, I/O pins are three-stated, and act asinput data pins14 Ground GND. Ground for the device28 Power Supply Vcc. Power supply for the deviceNotes:2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V Typ., T = 25°C, and t = 70 ns.CC CC A AA Document #: 38-05057 Rev. *D Page 2 of 13 CY62256VStatic Discharge Voltage...... > 2001VMaximum Ratings(per MIL-STD-883, Method 3015)(Above which the useful life may be impaired. For user guide-Latch-up Current....... > 200 mAlines, not tested.)Operating RangeStorage Temperature ......–65°C to +150°CAmbient Ambient Temperature withTemperature Power Applied–55°C to +125°C[4]Device Range (T ) VA CCSupply Voltage to Ground PotentialCY62256V Commercial 0°C to +70°C 2.7V to (Pin 28 to Pin 14) ....... –0.5V to +4.6V3.6VIndustrial −40°C to DC Voltage Applied to Outputs+85°C [3]in High-Z State –0.5V to V + 0.5VCCAutomotive −40°C to [3]DC Input Voltage ......–0.5V to V + 0.5VCC+125°C Output Current into Outputs (LOW) ..20 mACY62256V25 Commercial 0°C to +70°C 2.3V to 2.7VElectrical

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