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CY62256LL-70ZI from CYPRESS  , Cypress 22pcs , Alternate PN:CY62256LL70ZI,256K (32K x 8) Static RAM
Partno Mfg Dc Qty Available
CY62256LL-70ZI CYPRESS   N/a 22
CY62256LL-70ZI from CYP, Cypress 5120pcs , TSOP28 , Alternate PN:CY62256LL70ZI,256K (32K x 8) Static RAM
CY62256LL-70ZI from CYPRESS, Cypress 106pcs , TSOP-28 , Alternate PN:CY62256LL70ZI,256K (32K x 8) Static RAM

Block DiagramI/O0INPUTBUFFERI/O1A10A9I/O2A8A7I/OA36512 x 512A5ARRAYA I/O4 4A3A2I/O5CEI/O6POWERWE COLUMNDOWNDECODERI/O7OENote:1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.Cypress Semiconductor Corporation • 3901NorthFirstStreet • SanJose • • Document #: 38-05248 Rev. *C Revised June 25, 2004ROW DECODERA14A13A12A11A1A0SENSE AMPS CY62256Product PortfolioPower Dissipation Operating, I Standby, I CC SB2V Range (V) (mA) (µA)CC Speed [2] [2] [2]Product Min. Typ. Max. (ns) Typ. Max. Typ. Max.CY62256 Commercial 4.5 5.0 5.5 70 28 55 1 5CY62256L Com’l / Ind’l 55/70 25 50 2 50CY62256LL Commercial 70 25 50 0.1 5CY62256LL Industrial 55/70 25 50 0.1 10CY62256LL Automotive 55 25 50 0.1 15Pin Configurations 21AOE 220A 201 23 CE19I/OA 24Narrow SOIC 2 7DIP18 I/OA25 63Top ViewTop View17A I/O26 5416I/O27WE 415 I/OTSOP I 3A 28 V V 281 A 1 28 V5 CC 5 CC CC14 GNDA 15 Top ViewA 2 27 WEA 2 27 WE 136 A I/O6 2 26(not to scale)12A 26 3 I/O3 A 3 26 A7 17 A A4 7411A I/O4 08AA 4 A25 3 A 4 258 3 108 AA 5 14924 24 9A A A5 A A A 6 139 2 5 109 28AA 711 12A 23 AA 23 A10 6 110 6 122A OE 22A OE11 7 A11 7 7 8 A11 1221 A A 9A 21 A 6 A8 0 A 10 1312 8 01210 AA 51420 9A CE 209 A 9 CE1313A 11 I/O8 4 0A 19 TSOP I10 A 19 3 1214 I/O 10 A7 I/O14 I/O 17 713218 A Reverse Pinout I/O11 I/O 18 I/O 6 2I/O I/O 116 60 014GNDA 15 Top View1712 I/O 17 I/OI/O I/O 125 51 1 28 15 I/OV 3CC(not to scale)I/O 16 I/O 1613 I/O 13 16 I/O 272 4 I/O2 4 WE 417A 26 I/OI/O 4 5GND 15 GND 15 I/O14 314 318A 253 I/O619A 24 I/O2 723 20CEA122 21 AOE 0Pin DefinitionsPin Number Type Description1-10, 21, 23-26 Input A -A . Address Inputs0 1411-13, 15-19, Input/Output I/O -I/O . Data lines. Used as input or output lines depending on operation0 727 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ isconducted20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pinsbehave as outputs. When deasserted HIGH, I/O pins are three-stated, and act asinput data pins14 Ground GND. Ground for the device28 Power Supply Vcc. Power supply for the deviceNotes:2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.A CCDocument #: 38-05248 Rev. *C Page 2 of 12 CY62256Output Current into Outputs (LOW).. 20 mAMaximum RatingsStatic Discharge Voltage...... > 2001V(Above which the useful life may be impaired. For user guide-(per MIL-STD-883, Method 3015)lines, not tested.)Latch-up Current....... > 200 mAStorage Temperature ......–65°C to +150°COperating RangeAmbient Temperature withPower Applied.-55°C to +125°C[4]Range Ambient Temperature (T ) VA CCSupply Voltage to Ground PotentialCommercial 0°C to +70°C 5V ± 10%(Pin 28 to Pin 14) ....... –0.5V to +7.0VIndustrial –40°C to +85°C 5V ± 10%DC Voltage Applied to Outputs[3]Automotive –40°C to +125°C 5V ± 10%in High-Z State –0.5V to V + 0.5VCC[3]DC Input Voltage ......–0.5V to V + 0.5VCCElectrical featureswhile WE remains inactive or HIGH. Under these conditions,• TTL-compatible inputs and outputsthe contents of the location addressed by the information onaddress pins are present on the eight data input/output pins.• Automatic power-down when deselected• CMOS for optimum speed/power The input/output pins remain in a high-impedance state unlessthe chip is selected, outputs are enabled, and write enable• Package available in a standard 450-mil-wide (300-mil (WE) is HIGH.body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packagesLogic Block DiagramI/O0INPUTBUFFERI/O1A10A9I/O2A8A7I/OA36512 x 512A5ARRAYA I/O4 4A3A2I/O5CEI/O6POWERWE COLUMNDOWNDECODERI/O7OENote:1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.Cypress Semiconductor Corporation • 3901NorthFirstStreet • SanJose • • Document #: 38-05248 Rev. *C Revised June 25, 2004ROW DECODERA14A13A12A11A1A0SENSE AMPS CY62256Product PortfolioPower Dissipation Operating, I Standby, I CC SB2V Range (V) (mA) (µA)CC Speed [2] [2] [2]Product Min. Typ. Max. (ns) Typ. Max. Typ. Max.CY62256 Commercial 4.5 5.0 5.5 70 28 55 1 5CY62256L Com’l / Ind’l 55/70 25 50 2 50CY62256LL Commercial 70 25 50 0.1 5CY62256LL Industrial 55/70 25 50 0.1 10CY62256LL Automotive 55 25 50 0.1 15Pin Configurations 21AOE 220A 201 23 CE19I/OA 24Narrow SOIC 2 7DIP18 I/OA25 63Top ViewTop View17A I/O26 5416I/O27WE 415 I/OTSOP I 3A 28 V V 281 A 1 28 V5 CC 5 CC CC14 GNDA 15 Top ViewA 2 27 WEA 2 27 WE 136 A I/O6 2 26(not to scale)12A 26 3 I/O3 A 3 26 A7 17 A A4 7411A I/O4 08AA 4 A25 3 A 4 258 3 108 AA 5 14924 24 9A A A5 A A A 6 139 2 5 109 28AA 711 12A 23 AA 23 A10 6 110 6 122A OE 22A OE11 7 A11 7 7 8 A11 1221 A A 9A 21 A 6 A8 0 A 10 1312 8 01210 AA 51420 9A CE 209 A 9 CE1313A 11 I/O8 4 0A 19 TSOP I10 A 19 3 1214 I/O 10 A7 I/O14 I/O 17 713218 A Reverse Pinout I/O11 I/O 18 I/O 6 2I/O I/O 116 60 014GNDA 15 Top View1712 I/O 17 I/OI/O I/O 125 51 1 28 15 I/OV 3CC(not to scale)I/O 16 I/O 1613 I/O 13 16 I/O 272 4 I/O2 4 WE 417A 26 I/OI/O 4 5GND 15 GND 15 I/O14 314 318A 253 I/O619A 24 I/O2 723 20CEA122 21 AOE 0Pin DefinitionsPin Number Type Description1-10, 21, 23-26 Input A -A . Address Inputs0 1411-13, 15-19, Input/Output I/O -I/O . Data lines. Used as input or output lines depending on operation0 727 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ isconducted20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pinsbehave as outputs. When deasserted HIGH, I/O pins are three-stated, and act asinput data pins14 Ground GND. Ground for the device28 Power Supply Vcc. Power supply for the deviceNotes:2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.A CCDocument #: 38-05248 Rev. *C Page 2 of 12 CY62256Output Current into Outputs (LOW).. 20 mAMaximum RatingsStatic Discharge Voltage...... > 2001V(Above which the useful life may be impaired. For user guide-(per MIL-STD-883, Method 3015)lines, not tested.)Latch-up Current....... > 200 mAStorage Temperature ......–65°C to +150°COperating RangeAmbient Temperature withPower Applied.-55°C to +125°C[4]Range Ambient Temperature (T ) VA CCSupply Voltage to Ground PotentialCommercial 0°C to +70°C 5V ± 10%(Pin 28 to Pin 14) ....... –0.5V to +7.0VIndustrial –40°C to +85°C 5V ± 10%DC Voltage Applied to Outputs[3]Automotive –40°C to +125°C 5V ± 10%in High-Z State –0.5V to V + 0.5VCC[3]DC Input Voltage ......–0.5V to V + 0.5VCCElectrical
CY62256LL-70ZRI CYP, CY62256256K (32K x 8) Static RAM[1]

CY62256LL-70ZI ,256K (32K x 8) Static RAMBlock DiagramI/O0INPUTBUFFERI/O1A10A9I/O2A8A7I/OA36512 x 512A5ARRAYA I/O4 4A3A2I/O5CEI/O6POWERWE CO ..
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