CY2PP318JI ,1 of 2:8 Differential Clock/Data Fanout BufferBlock Diagram Pin ConfigurationQ0Q0#Q1Q1#VCCQ2CLKAQ2# Q0CLKB#CLKA#Q0#NCQ1Q7#Q3C Y 2P P 318VC CVEE V ..
CY2SSTV855ZC ,Differential Clock Buffer/DriverBlock Diagram Pin ConfigurationGND 1 28 GNDYC0 YC32 27YT0YC0YT0 YT33 26PWRDWNPowerdownVDDQ VDDQ4 25 ..
CY2SSTV855ZC ,Differential Clock Buffer/Driverapplications very-low-jitter zero-delay buffer that distributes a differentialclock input pair (SST ..
CY2SSTV855ZC ,Differential Clock Buffer/DriverFunctional Description• Phase-locked loop (PLL) clock distribution for Double The CY2SSTV855 is a h ..
CY2SSTV855ZXCT , Differential Clock Buffer/Driver
CY2SSTV855ZXCT , Differential Clock Buffer/Driver
D1005 , METAL GATE RF SILICON FET
D1018 , METAL GATE RF SILICON FET
D1020 , METAL GATE RF SILICON FET
D1022 , METAL GATE RF SILICON FET
D10AA10Z4 , Surface Mount Attenuator
D10AA10Z4 , Surface Mount Attenuator
CY2PP318JI
