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CHL8112ACHILN/a18887avaiDual Loop, 4+1 multiphase AMD PWM controller for high efficiency, highly accurate VR solutions
CHL8112B-00CRT |CHL8112B00CRTCHILN/a11avaiDual Loop, 4+1 multiphase AMD PWM controller for high efficiency, highly accurate VR solutions


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CHL8112A-CHL8112B-00CRT
Dual Loop, 4+1 multiphase AMD PWM controller for high efficiency, highly accurate VR solutions
@HJLLL
Semiconductor
PRODUC T BRIEF
DIGITAL MULTI-PHASE BUCK CONTROLLER
PRELIMINARY CHL81 1 2A/ B
FEATURES
q 5-phase dual output PWM Controller
q Phases are flexibly assigned between Loops 1 & 2
o AMD© SVl/G34 & Memory MPoL modes
a Dual OCP support for l-spike enhanced AMD CPUs
. SMB_A|ert Pin for Servers
. PMBus Address pin or Variable Gate Drive (CHL8112A)
q 2nd Temperature Sense (CHL8112B)
. Overclocking & Gaming Mode with Vmax setting
. Switching frequency from 200kHz to 1.2MHz per phase
0 CHiL Efficiency Shaping Features including Variable
Gate Drive (CHL8112A only), Dynamic Phase Control
q Programmable 1-phase or 2-phase for Light Loads and
Active Diode Emulation for Very Light Loads
o CHiL Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
q Designed for use with coupled inductors
. Auto-Phase Detection with auto-compensation
o Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
. |2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both loops
q Non-Volatile Memory (NVM) for custom configuration
q Compatible with CHiL ATL and 3.3V tri-state Drivers
q +3.3V supply voltage; (PC to 85% ambient operation
q Pb-Free, RoHS, 6x6 40 pin QFN package
DESCRIPTION
The CHL8112A/B are dual-loop digital multi-phase buck
controllers that drive up to 5 phases. The CHL8112A/B is
fully AMDO SVI compliant on both loops and provides a Vtt
tracking function for DDR memory.
NVM storage saves pins and enables a small package size.
The CHL8112A/B includes the CHiL Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. CHiL Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. CHiL Dynamic Phase Control
adds/drops active phases based upon load current. The
CHL8112A/B can be configured to enter 1-phase operation
and active diode emulation mode automatically or by
command.
CHiL's unique Adaptive Transient Algorithm (ATA), based
on proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors. In addition, a coupled inductor mode,
with phases added/dropped in pairs, enables further
improvement in transient response and form factor.
VFLREADY‘I -
VR_READY L2] -
/ PWFRJK2
The l2C/PMBus interface can communicate with up to 16
CHL8112A/B based VR loops. Device configuration and
fault parameters are easily defined using the CHiL Intuitive
Power Designer (IPD) GUI and stored in on-chip NVM.
The CHL8112A/B provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal.
The CHL8112A/B also includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its "set-and-forget" methodology.
VCC T:
VSEN -
VRTN - CHL8112A/B
Ll] 40 Pin 6x6 QFN
RRES - Top View
TSEN - i
V18A - i
PWRGD2 -
______
T,''brc'la'lnJsNu/eQu1aa"iri
zoov - 5jtsb(tl,'rst.r."-.'-.F.r-rjt;trpt,kr,c1o'
'fijffeerc5Rrsrsnrn),."0r-..E
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"Si,i,u-5rronS,i.irgi-','j'ci
CCUQ im II
"iiiaETtr, m m
’0 so E PA.,
a E to EN
Figure 1. CHL8112A & CHL8112B Packages
APPLICATIONS
o AMD© SVI based systems
. DDR Memory with Vtt tracking
q Overclocked & Gaming platforms
RCSP_L2
RCSM_L2
VSEN_L2
_ VRTN_L2
lif, PWM5
_ PWM3
Trademarks and registered trademarks are the property of the respective
owners.
PBOO12 Rev. 0.04, August 25, 2010

Page 1 of 2
One Highwood Drive, Tewksbury, MA 01876
Tel: +1(978)-640-0011
www.chilsemi.mm
© 2010 CHiL Semiconductor Corp. All rights reserved
_ Smkmdodod
PRODUCT BRIEF
DIGITAL MULTI-PHASE BUCK CONTROLLER
CHL8112A/B
TYPICAL APPLICATIONS BLOCK DIAGRAMS
9 NC'lSV02
RCSM ISEN1
RRES PWM2
VMCHL8112A
VR_RDCL1'/PvvRGDs Inma
VR_RDY_L21/Pwnot'
VINSEN
Nc‘NFIXEN2
NCVSVD2
15 VFLHOT#'/
VRHOTJCRIWZ
From 16
System EN
cc PU_LI
5m cHLssm
CN/GD "T-II C555 swam
T Egg mom.
cc PU_L2
FM'ERCS CCS - 135/ ______________ I
R“ 29 RCSM_L2 I T 'it" cm .5 l
27 VAFLGATL 20 l Triivi,i,, Sim H v V60:
26 xiizi: PM_ADDR l o" D WWW - l
Notes L _________ ttt1"l1i'tt'ltit_i
i,','),','),',',','),)),)',)'',',",,',',,',':'' GND
ORDERING INFORMATION
CHL8112 Cl - Package Tape & Reel Qty Part Number
QFN 3000 CHL8112A-OOCRT1
T: Tape & Reel QFN 3000 CHL8112A-xxCRT2
QFN 3000 CHL8112B-00CRTI
Package type QFN 3000 CHL8112B-xxCRT
R : QFN Notes
Operating Temperature l. For unprogrammed/default parts, use configuration
C: Commercial Standard file 00. Unprogrammed parts will not start up until
programmed in order to insure a safe power up.
xx: Configuration file 2. -xx indicates a customer specific configuration file
A: CHL8112A
B: CHL8112B
ChttrL,, Page 2 of 2 PBOO12

Rev. 0.04, August 25, 2010
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