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CDCV855-CDCV855-IPW-CDCV855IPWRG4-CDCV855PW-CDCV855PWR
1:4 DDR PLL Clock Driver
Low Jitter (cyc–cyc): ±50 ps Distributes One Differential Clock Input toFour Differential Clock Outputs Enters Low Power Mode and Three-State
Outputs When Input CLK Signal Is Less
Than 20 MHz or PWRDWN Is Low Operates From Dual 2.5-V Supplies 28-Pin TSSOP Package Consumes < 200-μA Quiescent Current External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
descriptionThe CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of
feedback clock outputs (FBOUT , FBOUT). When PWRDWN is high, the outputs switch in phase and frequency
with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is
shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below
a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit
detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the
PLL again and enables the outputs.
When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV855 is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONSPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VDDQ
GND
CLK
CLK
VDDQ
AVDD
AGND
VDDQ
GND
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
VDDQ
GND
