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CDCU877ARHARTIN/a519avai1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARHARG4TIN/a6avai1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877AZQLTTI/PBFN/a750avai1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications
CDCU877AZQLTTIN/a269avai1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications


CDCU877AZQLT ,1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM ApplicationsSCAS688D–JUNE 2005–REVISED JULY 2007TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME GQL/ZQL RHA/RTBAG ..
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CDCU877GQLT ,1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM ApplicationsFEATURES • Low Static Phase Offset: ±50 ps• 1.8-V Phase Lock Loop Clock Driver for • Distributes On ..
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CDCU877ARHAR-CDCU877ARHARG4-CDCU877AZQLT
1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications
www.ti.com
FEATURES
DESCRIPTION
CDCU877,, CDCU877A
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS688D–JUNE 2005–REVISED JULY 2007
Low Static Phase Offset: ±50ps 1.8-V Phase Lock Loop Clock Driver for Distributes One Differential Clock Inputto Ten
Double Data Rate (DDRII) Applications Differential Outputs
Spread Spectrum Clock Compatible 52-Ball μBGA (MicroStar™ Junior BGA,
0,65-mm pitch) and 40-Pin MLF
Operating Frequency:10 MHzto 400 MHz External Feedback Pins (FBIN, FBIN) are Used Low Current Consumption: <135 mA Synchronize the Outputsto the Input Low Jitter (Cycle-Cycle): ±30ps Clocks Low Output Skew:35 ps Meetsor Exceeds JESD82-8 PLL Standard for Low Period Jitter: ±20ps PC2-3200/4300 Low Dynamic Phase Offset: ±15 ps Fail-Safe Inputs
The CDCU877isa high-performance, low-jitter, low-skew, zero-delay buffer that distributesa differential clock
input pair (CK, CK)to ten differential pairof feedback clock
outputs (FBOUT, FBOUT). CK), the feedback clocks
(FBIN, FBIN), the LVCMOS When OEis low, the
clock outputs, except FBOUT/FBOUT,to maintain its locked-in
frequency. OS (output select) OSis high, OE functions previously described. When they are free running.
When AVDDis grounded, the PLLis turnedoff and bypassedfor test purposes.
When both clock inputs (CK, CK) are logic low, the device entersina low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performsina low
power state whereall outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic lowto being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
The CDCU877is ableto track spread spectrum clocking (SSC) for reduced EMI. This device operates from
—40°Cto 85°C.
ORDERING INFORMATION 52-BALL BGA(1) 40-Pin MLF

CDCU877ZQL CDCU877RHA
CDCU877AZQL CDCU877ARHA-40°Cto 85°C CDCU877GQL CDCU877RTB
CDCU877AGQL CDCU877ARTB
(1) Forthe most current package and ordering information, seethe
Package Option Addendumatthe endof this document,or seethe websiteat www.ti.com.
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