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CDC2510PWRTIN/a60avai3.3-V Phase-Lock Loop Clock Driver


CDC2510PWR ,3.3-V Phase-Lock Loop Clock Driver     SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004PW PACKAGE ..
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CDC2510PWR
3.3-V Phase-Lock Loop Clock Driver
Ten Outputs Single Output Enable Terminal Controls All
Ten Outputs
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3-V VCC Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package
description

The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V VCC and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2510 is characterized for operation from 0°C to 70°C.CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
1Y0
1Y1
1Y2
GNDCC
FBOUT
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