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CD74HCT251EHARRISN/a7279avaiHigh Speed CMOS Logic 8-Input Multiplexer, 3-State
CD74HCT251MTIBBN/a98avaiHigh Speed CMOS Logic 8-Input Multiplexer, 3-State
CD74HCT251M96TIN/a1161avaiHigh Speed CMOS Logic 8-Input Multiplexer, 3-State


CD74HCT251E ,High Speed CMOS Logic 8-Input Multiplexer, 3-StateFeatures Description• Selects One of Eight Binary Data Inputs The ’HC251 and ’HCT251 are 8-channel ..
CD74HCT251M ,High Speed CMOS Logic 8-Input Multiplexer, 3-StateCD54HC251, CD74HC251,CD54HCT251, CD74HCT251Data sheet acquired from Harris SemiconductorSCHS169CHig ..
CD74HCT251M96 ,High Speed CMOS Logic 8-Input Multiplexer, 3-StateMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT253E ,High Speed CMOS Logic Dual 4-Input MultiplexersMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HCT253M ,High Speed CMOS Logic Dual 4-Input MultiplexersFeatures Description• Common Select Inputs The CD74HC253 and CD74HCT253 are dual 4-to-1 lineselecto ..
CD74HCT257 ,High Speed CMOS Logic Quad 2-Input Multiplexers with Non-Inverting 3-State OutputsFeaturesMoving data from two groups of registers to four common• Buffered Inputsoutput buses is a c ..
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CL-205 , Infrared Emitting Diodes(GaAlAs)
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CD74HCT251E-CD74HCT251M-CD74HCT251M96
High Speed CMOS Logic 8-Input Multiplexer, 3-State
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251 SCHS169C High-Speed CMOS Logic November 1997 - Revised October 2003 8-Input Multiplexer, Three-State Features Description • Selects One of Eight Binary Data Inputs The ’HC251 and ’HCT251 are 8-channel digital multiplexers with three-state outputs, fabricated with high-speed silicon- • Three-State Output Capability [ /Title gate CMOS technology. Together with the low power (CD74 consumption of standard CMOS integrated circuits, they • True and Complement Outputs possess the ability to drive 10 LSTTL loads. The three-state HC251 • Typical (Data to Output) Propagation Delay of 14ns at feature makes them ideally suited for interfacing with bus o , = 5V, C = 15pF, T = 25 C V CC L A lines in a bus-oriented system. D74 C • Fanout (Over Temperature Range) This multiplexer features both true (Y) and complement (Y) HCT25 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads outputs as well as an output enable (OE) input. The OE must 1) - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads be at a low logic level to enable this device. When the OE input is high, both outputs are in the high-impedance state. /Sub- o o • Wide Operating Temperature Range . . . -55 C to 125 C When enabled, address information on the data select inputs ject determines which data input is routed to the Y and Y • Balanced Propagation Delay and Transition Times (High outputs. The ’HCT251 logic family is speed, function, and • Significant Power Reduction Compared to LSTTL Speed pin-compatible with the standard ’LS251. Logic ICs CMOS Ordering Information • Alternate Source is Philips Logic 8-Input • HC Types TEMP. RANGE o - 2V to 6V Operation Multi- PART NUMBER ( C) PACKAGE - High Noise Immunity: N = 30%, N = 30% of V plexer; IL IH CC CD54HC251F3A -55 to 125 16 Ld CERDIP at V = 5V CC Three- CD54HCT251F3A -55 to 125 16 Ld CERDIP • HCT Types - 4.5V to 5.5V Operation CD74HC251E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HC251M -55 to 125 16 Ld SOIC V = 0.8V (Max), V = 2V (Min) IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V CD74HC251MT -55 to 125 16 Ld SOIC l OL OH CD74HC251M96 -55 to 125 16 Ld SOIC CD74HCT251E -55 to 125 16 Ld PDIP Pinout CD74HCT251M -55 to 125 16 Ld SOIC CD54HC251, CD54HCT251 (CERDIP) CD74HCT251MT -55 to 125 16 Ld SOIC CD74HC251, CD74HCT251 (PDIP, SOIC) CD74HCT251M96 -55 to 125 16 Ld SOIC TOP VIEW NOTE: When ordering, use the entire part number. The suffix 96 I 1 16 V 3 CC denotes tape and reel. The suffix T denotes a small-quantity reel of 250. I 2 15 I 2 4 I 3 14 I 1 5 I 4 13 I 0 6 Y 5 12 I 7 Y 6 11 S0 OE 7 10 S1 GND 8 9 S2 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
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