CD74HC4514M ,High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input LatchesFeatures Description• Multifunction Capability The CD54HC4514, CD74HC4514, and CD74HC4515 arehigh-s ..
CD74HC4515EN , High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches
CD74HC4515M ,High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input LatchesFeatures Description• Multifunction Capability The CD54HC4514, CD74HC4514, and CD74HC4515 arehigh-s ..
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CD74HC4538E ,High Speed CMOS Logic Dual Retriggerable Precision Monostable MultivibratorsMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
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CD74HC4514M
High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches
CD54HC4514, CD74HC4514, CD74HC4515 SCHS280C High-Speed CMOS Logic 4- to 16-Line November 1997 - Revised July 2003 Decoder/Demultiplexer with Input Latches Features Description • Multifunction Capability The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed - Binary to 1-of-16 Decoder [ /Title latch and a 4- to 16-line decoder. The selected output is - 1-to-16 Line Demultiplexer enabled by a low on the enable input (E). A high on E inhibits (CD74 • Fanout (Over Temperature Range) selection of any output. Demultiplexing is accomplished by HC451 using the E input as the data input and the select inputs (A0- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads 4, A3) as addresses. This E input also serves as a chip select - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74 when these devices are cascaded. o o • Wide Operating Temperature Range . . . -55 C to 125 C HC451 When Latch Enable (LE) is high the output follows changes 5) • Balanced Propagation Delay and Transition Times in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level /Sub- • Significant Power Reduction Compared to LSTTL (high for the 4514, low for the 4515) it had before the latches ject Logic ICs were enabled. These devices, enhanced versions of the (High • HC Types equivalent CMOS types, can drive 10 LSTTL loads. Speed - 2V to 6V Operation Ordering Information CMOS = 30%, N = 30% of V - High Noise Immunity: N IL IH CC at V = 5V CC o PART NUMBER TEMP. RANGE ( C) PACKAGE CD54HC4514F3A -55 to 125 24 Ld CERDIP Pinout CD74HC4514E -55 to 125 24 Ld PDIP CD54HC4514 (CERDIP) CD74HC4514EN -55 to 125 24 Ld PDIP CD74HC4514, CD74HC4515 (PDIP, SOIC) CD74HC4514M -55 to 125 24 Ld SOIC TOP VIEW CD74HC4514M96 -55 to 125 24 Ld SOIC LE 1 24 CD74HC4515E -55 to 125 24 Ld PDIP V CC A0 2 23 E CD74HC4515EN -55 to 125 24 Ld PDIP A1 3 22 A3 CD74HC4515M -55 to 125 24 Ld SOIC Y7 4 21 A2 Y6 5 20 Y10 CD74HC4515M96 -55 to 125 24 Ld SOIC Y5 6 19 Y11 NOTE: When ordering, use the entire part number. The suffix 96 Y4 7 18 Y8 denotes tape and reel. Y3 8 17 Y9 Y1 9 16 Y14 Y2 10 15 Y15 Y0 11 14 Y12 GND 12 13 Y13 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
