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CD74HC4040-CD74HC4040E-CD74HC4040M-CD74HC4040M96 Fast Delivery,Good Price
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CD74HC4040HARRISN/a489avaiHigh Speed CMOS Logic 12-Stage Binary Counter
CD74HC4040EHARN/a202avaiHigh Speed CMOS Logic 12-Stage Binary Counter
CD74HC4040MTIN/a21avaiHigh Speed CMOS Logic 12-Stage Binary Counter
CD74HC4040MTI,TIN/a21avaiHigh Speed CMOS Logic 12-Stage Binary Counter
CD74HC4040M96HARRISN/a2277avaiHigh Speed CMOS Logic 12-Stage Binary Counter
CD74HC4040M96TIN/a530avaiHigh Speed CMOS Logic 12-Stage Binary Counter


CD74HC4040M96 ,High Speed CMOS Logic 12-Stage Binary CounterCD54HC4040, CD74HC4040,CD54HCT4040, CD74HCT4040Data sheet acquired from Harris SemiconductorSCHS203 ..
CD74HC4040M96 ,High Speed CMOS Logic 12-Stage Binary CounterCD54HC4040, CD74HC4040,CD54HCT4040, CD74HCT4040Data sheet acquired from Harris SemiconductorSCHS203 ..
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CD74HC4046AM ,High Speed CMOS Logic Phase-Locked-Loop with VCOGeneral DescriptionVCO Phase ComparatorsThe signal input (SIG ) can be directly coupled to the self ..
CD74HC4046AM96 ,High Speed CMOS Logic Phase-Locked-Loop with VCOGeneral DescriptionVCO Phase ComparatorsThe signal input (SIG ) can be directly coupled to the self ..
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CD74HC4040-CD74HC4040E-CD74HC4040M-CD74HC4040M96
High Speed CMOS Logic 12-Stage Binary Counter
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 SCHS203D High-Speed CMOS Logic February 1998 - Revised October 2003 12-Stage Binary Counter Features Description • Fully Static Operation The ’HC4040 and ’HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flip- • Buffered Inputs [ /Title flops. The state of the stage advances one count on the (CD74H negative clock transition of each input pulse; a high voltage • Common Reset level on the MR line resets all counters to their zero state. All C4040, • Negative Edge Pulsing inputs and outputs are buffered. CD74HC • Fanout (Over Temperature Range) T4040) Ordering Information - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads /Subject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TEMP. RANGE (High o PART NUMBER ( C) PACKAGE o o C to 125 C • Wide Operating Temperature Range . . . -55 Speed CD54HC4040F3A -55 to 125 16 Ld CERDIP CMOS • Balanced Propagation Delay and Transition Times Logic CD54HCT4040F3A -55 to 125 16 Ld CERDIP • Significant Power Reduction Compared to LSTTL 12-Stage Logic ICs CD74HC4040E -55 to 125 16 Ld PDIP Binary • HC Types CD74HC4040M -55 to 125 16 Ld SOIC - 2V to 6V Operation CD74HC4040MT -55 to 125 16 Ld SOIC - High Noise Immunity: N = 30%, N = 30% of V IL IH CC at V = 5V CC CD74HC4040M96 -55 to 125 16 Ld SOIC • HCT Types CD74HC4040NSR -55 to 125 16 Ld SOP - 4.5V to 5.5V Operation CD74HCT4040E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) IL IH CD74HCT4040M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HCT4040MT -55 to 125 16 Ld SOIC CD74HCT4040M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4040, CD54HCT4040 (CERDIP) CD74HC4040 (PDIP, SOIC, SOP) CD74HCT4040 (PDIP, SOIC) TOP VIEW Q 1 16 V CC 12 Q 2 15 Q 6 11 Q 3 14 Q 5 10 Q7 4 13 Q 8 Q 5 12 Q 4 9 Q 6 11 MR 3 10 CP Q 7 2 9 Q ‘ GND 8 1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
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