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CD74HC4015EN/a65avaiHigh Speed CMOS Logic Dual 4-Stage Static Shift Registers
CD74HC4015EHARRISN/a88avaiHigh Speed CMOS Logic Dual 4-Stage Static Shift Registers


CD74HC4015E ,High Speed CMOS Logic Dual 4-Stage Static Shift RegistersMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD74HC4015E ,High Speed CMOS Logic Dual 4-Stage Static Shift RegistersFeatures Description• Maximum Frequency, Typically 60MHz The ’HC4015 consists of two identical, ind ..
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CD74HC4015E
High Speed CMOS Logic Dual 4-Stage Static Shift Registers
CD54HC4015, CD74HC4015 SCHS198C High Speed CMOS Logic November 1997 - Revised May 2003 Dual 4-Stage Static Shift Register Features Description • Maximum Frequency, Typically 60MHz The ’HC4015 consists of two identical, independent, 4-stage o C = 15pF, V = 5V, T = 25 C serial-input/parallel-output registers. Each register has L CC A [ /Title independent Clock (CP) and Reset (MR) inputs as well as a • Positive-Edge Clocking single serial Data input. “Q” outputs are available from each (CD74 of the four stages on both registers. All register stages are D- • Overriding Reset HC401 type, master-slave flip-flops. The logic level present at the 5) • Buffered Inputs and Outputs Data input is transferred into the first register stage and /Sub- shifted over one stage at each positive- going clock • Fanout (Over Temperature Range) transition. Resetting of all stages is accomplished by a high ject - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads level on the reset line. (High - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The device can drive up to 10 low power Schottky equivalent Speed o o C to 125 C • Wide Operating Temperature Range . . . -55 loads. The ’HC4015 is an enhanced version of equivalent CMOS CMOS types. • Balanced Propagation Delay and Transition Times Logic Dual • Significant Power Reduction Compared to LSTTL Ordering Information Logic ICs 4- o PART NUMBER TEMP. RANGE ( C) PACKAGE • HC Types - 2V to 6V Operation CD54HC4015F3A -55 to 125 16 Ld CERDIP - High Noise Immunity: N = 30%, N = 30% of V IL IH CC CD74HC4015E -55 to 125 16 Ld PDIP at V = 5V CC CD74HC4015M -55 to 125 16 Ld SOIC Pinout CD54HC4015 (CERDIP) CD74HC4015 (PDIP, SOIC) TOP VIEW 2CP 1 16 V CC 2Q 2 15 2D 3 1Q 3 14 2MR 2 1Q 4 13 2Q 1 0 1Q 5 12 2Q 0 1 1MR 6 11 2Q 2 1D 7 10 1Q 3 GND 8 9 1CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
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