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CD74ACT175E-CD74ACT175M-CD74ACT175M96 Fast Delivery,Good Price
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CD74ACT175ETIN/a1000avaiQuad D-Type Flip-Flops with Reset
CD74ACT175EHARN/a211avaiQuad D-Type Flip-Flops with Reset
CD74ACT175EHARRISN/a560avaiQuad D-Type Flip-Flops with Reset
CD74ACT175MHARRISN/a55avaiQuad D-Type Flip-Flops with Reset
CD74ACT175MHARN/a3333avaiQuad D-Type Flip-Flops with Reset
CD74ACT175M96TIN/a10000avaiQuad D-Type Flip-Flops with Reset


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CD74ACT175E-CD74ACT175M-CD74ACT175M96
Quad D-Type Flip-Flops with Reset
Speed of Bipolar F, AS, and S, WithSignificantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description/ordering information

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
CLK
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