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CD74AC112E-CD74AC112M-CD74AC112M96-CD74AC112M96G4 Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
CD74AC112ETIN/a1786avaiDual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
CD74AC112MHARRISN/a1136avaiDual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
CD74AC112M96TIN/a2400avaiDual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
CD74AC112M96G4TIN/a1556avaiDual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125


CD74AC112M96 ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS325 – JAN ..
CD74AC112M96G4 ,Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125logic diagram (positive logic)Q QPRE CLRK JCLK†absolute
CD74AC138E ,3-Line to 8-Line Inverting Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CD74AC138M96 ,3-Line to 8-Line Inverting Decoders/Demultiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CD74AC138M96 ,3-Line to 8-Line Inverting Decoders/Demultiplexerslogic diagram (positive logic)15Y01A14Y113Y22SelectBInputs12Y3DataOutputs11Y43C10Y59Y647G2AY7Enable ..
CD74AC138M96G4 ,3-Line to 8-Line Inverting Decoders/Demultiplexers 16-SOIC -55 to 125 CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS328A – JANUARY 2003 – REVISED FE ..
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CD74AC112E-CD74AC112M-CD74AC112M96-CD74AC112M96G4
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
Balanced Propagation Delays ±24-mA Output Drive Current– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
1PRE
GND
2CLR
2CLK
2PRE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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