CD54HCT173F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State OutputsMaximum Ratings Thermal InformationDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT173F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State OutputsCD54HC173, CD74HC173,CD54HCT173, CD74HCT173Data sheet acquired from Harris SemiconductorSCHS158EHig ..
CD54HCT174F ,High Speed CMOS Logic Hex D-Type Flip-Flops with ResetMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HCT174F3A ,High Speed CMOS Logic Hex D-Type Flip-Flops with ResetLogic DiagramCCLL ONE OF SIX F/F3 (4, 6, 11, 13, 14) Dp pDnn nCC LLCCLLppnnC CL LCLC 2 (5, 7, 10, 1 ..
CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetFeaturesLSTTL devices.• Common Clock and Asynchronous Reset on FourInformation at the D input is tr ..
CD54HCT175F3A ,High Speed CMOS Logic Quad D-Type Flip-Flops with ResetCD54HC175, CD74HC175,CD54HCT175, CD74HCT175Data sheet acquired from Harris SemiconductorSCHS160CHig ..
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CD54HCT173F3A
High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 SCHS158E High-Speed CMOS Logic February 1998 - Revised October 2003 Quad D-Type Flip-Flop, Three-State Features Description The ’HC173 and ’HCT173 high speed three-state quad D- • Three-State Buffered Outputs type flip-flops are fabricated with silicon gate CMOS technol- • Gated Input and Output Enables [ /Title ogy. They possess the low power consumption of standard • Fanout (Over Temperature Range) CMOS Integrated circuits, and can operate at speeds com- (CD74H parable to the equivalent low power Schottky devices. The - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads C173, buffered outputs can drive 15 LSTTL loads. The large output - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74H drive capability and three-state feature make these parts ide- o o C to 125 C • Wide Operating Temperature Range . . . -55 ally suited for interfacing with bus lines in bus oriented sys- CT173) • Balanced Propagation Delay and Transition Times tems. /Subject • Significant Power Reduction Compared to LSTTL The four D-type flip-flops operate synchronously from a com- (High Logic ICs mon clock. The outputs are in the three-state mode when Speed • HC Types either of the two output disable pins are at the logic “1” level. CMOS - 2V to 6V Operation The input ENABLES allow the flip-flops to remain in their = 30%, N = 30% of V - High Noise Immunity: N Logic IL IH CC present states without having to disrupt the clock If either of at V = 5V CC the 2 input ENABLES are taken to a logic “1” level, the Q Quad D- • HCT Types outputs are fed back to the inputs, forcing the flip-flops to Type remain in the same state. Reset is enabled by taking the - 4.5V to 5.5V Operation MASTER RESET (MR) input to a logic “1” level. The data - Direct LSTTL Input Logic Compatibility, V = 0.8V (Max), V = 2V (Min) outputs change state on the positive going edge of the clock. IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH The ’HCT173 logic family is functionally, as well as pin com- patible with the standard LS logic family. Ordering Information Pinout CD54HC173, CD54HCT173 TEMP. RANGE o (CERDIP) PART NUMBER ( C) PACKAGE CD74HC173 CD54HC173F3A -55 to 125 16 Ld CERDIP (PDIP, SOIC, SOP, TSSOP) CD74HCT173 CD54HCT173F3A -55 to 125 16 Ld CERDIP (PDIP, SOIC) TOP VIEW CD74HC173E -55 to 125 16 Ld PDIP OE 1 16 V CC CD74HC173M -55 to 125 16 Ld SOIC OE2 2 15 MR CD74HC173MT -55 to 125 16 Ld SOIC Q 3 14 D0 0 CD74HC173M96 -55 to 125 16 Ld SOIC Q 4 13 D1 1 Q 5 12 D2 CD74HC173NSR -55 to 125 16 Ld SOP 2 Q 6 11 D3 3 CD74HC173PW -55 to 125 16 Ld TSSOP CP 7 10 E2 CD74HC173PWR -55 to 125 16 Ld TSSOP GND 8 9 E1 CD74HC173PWT -55 to 125 16 Ld TSSOP CD74HCT173E -55 to 125 16 Ld PDIP CD74HCT173M -55 to 125 16 Ld SOIC CD74HCT173MT -55 to 125 16 Ld SOIC CD74HCT173M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
