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CD54HC85F3ATIN/a500avaiHigh Speed CMOS Logic 4-Bit Magnitude Comparator
CD54HC85F3A. |CD54HC85F3ATIN/a70avaiHigh Speed CMOS Logic 4-Bit Magnitude Comparator


CD54HC85F3A. ,High Speed CMOS Logic 4-Bit Magnitude ComparatorCD54HC85, CD74HC85,CD54HCT85, CD74HCT85Data sheet acquired from Harris SemiconductorSCHS136EHigh-Sp ..
CD54HC86F3A ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesMaximum Ratings Thermal InformationoDC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . ..
CD54HC86F3A. ,High Speed CMOS Logic Quad 2-Input EXCLUSIVE OR GatesCD54HC86, CD74HC86,CD54HCT86, CD74HCT86Data sheet acquired from Harris SemiconductorSCHS137DHigh-Sp ..
CD54HCT00 ,High Speed CMOS Logic Quad 2-Input NAND GatesFeatures Description• Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, andCD74HCT00 logic gates u ..
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CD54HCT00F. ,High Speed CMOS Logic Quad 2-Input NAND GatesCD54HC00, CD74HC00,CD54HCT00, CD74HCT00Data sheet acquired from Harris SemiconductorSCHS116CHigh-Sp ..
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CD54HC85F3A-CD54HC85F3A.
High Speed CMOS Logic 4-Bit Magnitude Comparator
CD54HC85, CD74HC85, CD54HCT85, CD74HCT85 SCHS136E High-Speed CMOS Logic 4-Bit Magnitude Comparator August 1997 - Revised October 2003 Features Description • Buffered Inputs and Outputs The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to • Typical Propagation Delay: 13ns (Data to Output at [ /Title achieve operating speeds similar to LSTTL with the low o V = 5V, C = 15pF, T = 25 C CC L A (CD74 power consumption of standard CMOS integrated circuits. • Serial or Parallel Expansion Without External Gating HC85, These 4-bit devices compare two binary, BCD, or other CD74 monotonic codes and present the three possible magnitude • Fanout (Over Temperature Range) results at the outputs (A > B, A < B, and A = B). The 4-bit HCT85 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads input words are weighted (A0 to A3 and B0 to B3), where A3 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ) and B are the most significant bits. 3 o o Sub- / • Wide Operating Temperature Range . . . -55 C to 125 C The devices are expandable without external gating, in both ject serial and parallel fashion. The upper part of the truth table • Balanced Propagation Delay and Transition Times (High indicates operation using a single device or devices in a • Significant Power Reduction Compared to LSTTL serially expanded application. The parallel expansion Speed Logic ICs scheme is described by the last three entries in the truth CMOS table. • HC Types Logic - 2V to 6V Operation Ordering Information 4-Bit - High Noise Immunity: N = 30%, N = 30%of V at IL IH CC Magni- V = 5V TEMP. RANGE CC o tude PART NUMBER ( C) PACKAGE • HCT Types Com- CD54HC85F3A -55 to 125 16 Ld CERDIP - 4.5V to 5.5V Operation para- - Direct LSTTL Input Logic Compatibility, CD54HCT85F3A -55 to 125 16 Ld CERDIP V = 0.8V (Max), V = 2V (Min) IL IH CD74HC85E -55 to 125 16 Ld PDIP - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC85M -55 to 125 16 Ld SOIC Pinout CD74HC85MT -55 to 125 16 Ld SOIC CD54HC85, CD54HCT85 (CERDIP) CD74HC85M96 -55 to 125 16 Ld SOIC CD74HC85 (PDIP, SOIC, SOP, TSSOP) CD74HCT85 (PDIP, SOIC) CD74HC85NSR -55 to 125 16 Ld SOP TOP VIEW CD74HC85PW -55 to 125 16 Ld TSSOP B3 1 16 V CC CD74HC85PWR -55 to 125 16 Ld TSSOP (A < B) IN 2 15 A3 (A = B) IN 3 14 B2 CD74HC85PWT -55 to 125 16 Ld TSSOP (A > B) IN 4 13 A2 CD74HCT85E -55 to 125 16 Ld PDIP (A > B) OUT 5 12 A1 CD74HCT85M -55 to 125 16 Ld SOIC (A = B) OUT 6 11 B1 CD74HCT85MT -55 to 125 16 Ld SOIC (A < B) OUT 7 10 A0 GND 8 9 B0 CD74HCT85M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, 1
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