CD54HC138F. ,High Speed CMOS Logic Inverting and Non-Inverting 3-to-8 Line Decoder DemultiplexerCD54/74HC138, CD54/74HCT138,CD54/74HC238, CD54/74HCT238Data sheet acquired from Harris Semiconducto ..
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CD54HC138F-CD54HC138F.-CD54HC138F3A
High Speed CMOS Logic Inverting and Non-Inverting 3-to-8 Line Decoder Demultiplexer
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 SCHS147I High-Speed CMOS Logic 3- to 8-Line Decoder/ October 1997 - Revised August 2004 Demultiplexer Inverting and Noninverting Features Ordering Information • Select One Of Eight Data Outputs TEMP. RANGE Active Low for 138, Active High for 238 o PART NUMBER ( C) PACKAGE [ /Title • l/O Port or Memory Selector CD54HC138F3A -55 to 125 16 Ld CERDIP (CD74 • Three Enable Inputs to Simplify Cascading HC138 CD54HC238F3A -55 to 125 16 Ld CERDIP = 5 V, • Typical Propagation Delay of 13 ns at V , CC o CD54HCT138F3A -55 to 125 16 Ld CERDIP C = 15 pF, T = 25 C L A D74 C CD54HCT238F3A -55 to 125 16 Ld CERDIP • Fanout (Over Temperature Range) HCT13 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads 8, CD74HC138E -55 to 125 16 Ld PDIP - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads CD74 CD74HC138M -55 to 125 16 Ld SOIC o o • Wide Operating Temperature Range . . . -55 C to 125 C HC238 CD74HC138MT -55 to 125 16 Ld SOIC , • Balanced Propagation Delay and Transition Times CD74HC138M96 -55 to 125 16 Ld SOIC D74 C • Significant Power Reduction Compared to LSTTL HCT23 Logic ICs CD74HC238E -55 to 125 16 Ld PDIP 8) • HC Types CD74HC238M -55 to 125 16 Ld SOIC /Sub- - 2 V to 6 V Operation CD74HC238MT -55 to 125 16 Ld SOIC ject - High Noise Immunity: N = 30%, N = 30% of V IL IH CC (High at V = 5 V CD74HC238M96 -55 to 125 16 Ld SOIC CC Speed • HCT Types CD74HC238NSR -55 to 125 16 Ld SOP - 4.5-V to 5.5-V Operation CD74HC238PW -55 to 125 16 Ld TSSOP - Direct LSTTL Input Logic Compatibility, V = 0.8 V (Max), V = 2 V (Min) CD74HC238PWR -55 to 125 16 Ld TSSOP IL IH - CMOS Input Compatibility, I ≤ 1µA at V , V l OL OH CD74HC238PWT -55 to 125 16 Ld TSSOP CD74HCT138E -55 to 125 16 Ld PDIP Description CD74HCT138M -55 to 125 16 Ld SOIC The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed silicon-gate CMOS decoders well suited to memory address CD74HCT138MT -55 to 125 16 Ld SOIC decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS CD74HCT138M96 -55 to 125 16 Ld SOIC circuitry, yet have speeds comparable to low-power Schottky CD74HCT238E -55 to 125 16 Ld PDIP TTL logic. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine CD74HCT238M -55 to 125 16 Ld SOIC which one of the eight normally high outputs of the HC/HCT138 series go low or which of the normally low CD74HCT238M96 -55 to 125 16 Ld SOIC outputs of the HC/HCT238 series go high. NOTE: When ordering, use the entire part number. The suffixes 96 Two active low and one active high enables (E1, E2, and E3) and R denote tape and reel. The suffix T denotes a small-quantity are provided to ease the cascading of decoders. The reel of 250. decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, 1
