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CD54AC74F3AHARRISN/a10avaiDual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
CD54AC74F3AIDTN/a300avaiDual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
CD54AC74F3AHAR?N/a10avaiDual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset


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CD54AC74F3A
Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset
Balanced Propagation Delays ±24-mA Output Drive Current– Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1CLK
1PRE
GND
2CLK
2PRE
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