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Partno Mfg Dc Qty AvailableDescript
CD4073BEHARRIS.N/a9avaiCMOS Triple 3-Input AND Gate
CD4073BMTIN/a290avaiCMOS Triple 3-Input AND Gate
CD4073BM96TIN/a25556avaiCMOS Triple 3-Input AND Gate
CD4073BNSRTIN/a1003avaiCMOS Triple 3-Input AND Gate
CD4073BPWTIN/a43avaiCMOS Triple 3-Input AND Gate
CD4073BPWRTIN/a2000avaiCMOS Triple 3-Input AND Gate


CD4073BM96 ,CMOS Triple 3-Input AND GateMAXIMUM RATINGS. AtistguteeMaximum Values:DC SUPPLY-VOLTAGE RANGE. (VDD)Voltages Iefermeua tovstsra ..
CD4073BNSR ,CMOS Triple 3-Input AND GateELECTRICAL CHARACTERISTICS atTA=250C, Input trrtf--20 ns,and cL=so préafzoo kitALL TYPESTesTcoumnon ..
CD4073BPW ,CMOS Triple 3-Input AND GateFeatures: Cl Medium-Speed Operation - tPLH,CMOS AND Gates‘PHL " 60 ns (tpr at VDD " 10 VHigh-Voltag ..
CD4073BPWR ,CMOS Triple 3-Input AND GateLogic diagram for 0040818 (I of 4 identical gates). od,-,,,," mum: l,,,sacs -Fig. 6 - Minimum outpu ..
CD4075B ,CMOS Triple 3-Input OR Gatecn4o713, ciraorsta, c040753 TypesCMOS OR Gates
CD4075BE ,CMOS Triple 3-Input OR GateMAXIMUM RATINGS, Absolute-Maximum Values:DC SUPPLY-VOLTAGE RANGE, (V00)" must" VEI'ERAYIIRE (I‘l-zs ..
CFH 400 , Low-Noise, High-Linearity Packaged pHEMT FET
CFH120-08 ,Preliminary DatasheetCharacteristics Symbol Max. Value UnitDrain-source voltage V 3.0 VDSDrain-gate voltage V 4.0 VDGGat ..
CFH120-08 ,Preliminary DatasheetGaAs HEMT CFH120___________________________________________________________________________________ ..
CFH120-08 ,Preliminary DatasheetFeatures· low noise pseudomorphic HEMTwith high associated gain· low cost plastic package· for low ..
CFH800 , Typical Common Source S - Parameters
CFK0301 , High Dynamic Range Dual, Low Noise GaAs FET


CD4073BE-CD4073BM-CD4073BM96-CD4073BNSR-CD4073BPW-CD4073BPWR
CMOS Triple 3-Input AND Gate
SCHS057C – Revised September 2003 The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). Copyright  2003,
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