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CD4030CNHARN/a40avaiQuad EXCLUSIVE-OR Gate
CD4030CNNSN/a243avaiQuad EXCLUSIVE-OR Gate
CD4030CNPHILPSN/a6avaiQuad EXCLUSIVE-OR Gate


CD4030CN ,Quad EXCLUSIVE-OR GateGeneral Description High noise immunity 0.45 V (typ.)CCThe CD4030C EXCLUSIVE-OR gates are monolithi ..
CD4030CN ,Quad EXCLUSIVE-OR GateElectrical CharacteristicsLimitsSymbol Parameter Conditions - 40°C +25°C +85°CUnitsMin Typ Max Min ..
CD4030CN ,Quad EXCLUSIVE-OR GateElectrical Characteristics tables provide conditionsfor actual device operation. Dual-In-Line 700 m ..
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CD4033BE ,CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Ripple BlankingMAXIMUM RATINGS, Absalute-Maximum Values:DC SUPPLY-VOLTAGE RANGE, (VDD)Voltages referenced to vss T ..
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CD4030CN
Quad EXCLUSIVE-OR Gate
CD4030C Quad EXCLUSIVE-OR Gate October 1987 Revised January 1999 CD4030C Quad EXCLUSIVE-OR Gate t = t = 40 ns (typ.) at C = 15 pF, 10V supply PHL PLH L General Description � High noise immunity 0.45 V (typ.) CC The CD4030C EXCLUSIVE-OR gates are monolithic com- plementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. All Applications inputs are protected against static discharge with diodes to • Automotive V and V . DD SS • Data terminals • Instrumentation Features • Medical electronics � Wide supply voltage range: 3.0V to 15V • Industrial controls � Low power: 100 nW (typ.) • Remote metering � Medium speed operation: • Computers Ordering Code: Order Number Package Number Package Description CD4030CSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4030CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP and SOP A B J 0 0 0 1 0 1 0 1 1 1 1 0 1 = HIGH Level 0 = LOW Level © 1999 DS005961.prf
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